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參數(shù)資料
| 型號(hào)： | K3S7V2000M-TC30 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 64M-Bit (4Mx16 /2Mx32) Synchronous MASKROM |
| 中文描述： | 6400位（4Mx16 / 2Mx32）同步MASKROM |
| 文件頁(yè)數(shù)： | 5/27頁(yè) |
| 文件大?。?/td> | 1080K |
| 代理商： | K3S7V2000M-TC30 |
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K3S7V2000M-TC
Synch. MROM
AC OPERATING TEST CONDITIONS
(T
A
= 0 to 70
°
C, V
DD
= 3.3V
±
0.3V, unless otherwise noted.)
Note : If CLK transition time is longer than 1ns, timing parameters should be compensated. Add [(tr+tf)/2-1]ns for transition time longer than 1ns. Transi-
tion time is measured between V
IL
(Max) and V
IH
(Min).
Parameter
Value
Timing Reference Levels of Input/Output Signals
1.4V
Input Signal Levels
V
IH
/V
IL
=2.4V/0.4V
Transition Time (Rise & Fall) of Input Signals
tr/tf=1ns/1ns
Output Load
LVTTL
3.3V
1200
870
Output
50pF
V
OH
(DC)=2.4V, I
OH
=-2mA
V
OL
(DC)=0.4V, I
OL
=2mA
Vtt=1.4V
50
Output
50pF
Z
0
=50
(Fig. 2) AC Output Load Circuit
(Fig. 1) DC Output Load Circuit
(AC operating conditions unless otherwise noted)
Note :
1. These t
RC
values are for BL=8. For BL=4, t
RC
=6 clks for up to 100MHz, t
RC
=6 clks for up to 83MHz, t
RC
=4 clks for up to 66MHz, t
RC
=4 clks for up to
50MHz, and t
RC
=3 clks for up to 33MHz.
RAS latency increase means, a simultaneous t
RC
increase in the same number of cycles.
( If RAS latency is 3 clks, t
RC
is 12 clks for BL=8.) Refer to attached technical note for gapless operation.
2. These
t
VCVC
values are for BL=8. For BL=4,
t
VCVC
=4clks for up to 100MHz,
t
VCVC
=4clks for up to 83MHz,
t
VCVC
=3clks for up to 66MHz,
t
VCVC
=3clks for
up to 50MHz, and
t
VCVC
=2clks for up to 33MHz.
Refer to attached technical note for gapless operation.
Parameter
Symbol
up to 100MHz
up to 83MHz
up to 66MHz
up to 50 Mhz
Unit
Notes
Min
Max
Min
Max
Min
Max
Min
Max
CLK Cycle Time
t
CC
10
12
15
-
20
-
ns
CLK to Valid Output Delay
t
SAC
-
6
-
6
-
6
-
6
ns
Data Output Hold Time
t
OH
2
-
2
-
2
-
2
-
ns
CLK High Pulse Width
t
CH
3
-
3.5
-
4
-
6.5
-
ns
CLK Low Pulse Width
t
CL
3
-
3.5
-
4
-
6.5
-
ns
Row-active to Row-active
t
RC
10
-
10
-
8
-
8
-
clks
1
Input Setup Time
t
SS
2
-
3
-
4
-
4
-
ns
Input Hold Time
t
SH
1
-
1
-
2
-
2
-
ns
CLK to Output in Low-Z
t
SLZ
0
-
0
-
0
-
0
-
ns
CLK to Output in High-Z
t
SHZ
-
7
-
8
-
10
-
15
ns
Transition Time
t
T
0.1
10
0.1
10
0.1
10
0.1
10
ns
Valid CAS Enable to Valid
CAS Enable
t
VCVC
8
-
8
-
7
-
7
-
clks
2
OPERATING AC PARAMETERS
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