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參數(shù)資料
| 型號(hào)： | K1S6416BCC |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 4Mx16 bit Page Mode Uni-Transistor Random Access Memory |
| 中文描述： | 4Mx16位頁(yè)面模式統(tǒng)一晶體管隨機(jī)存取存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 7/10頁(yè) |
| 文件大小： | 146K |
| 代理商： | K1S6416BCC |
Revision 1.0
April 2005
K1S6416BCC
- 7 -
U
t
RAM
Address
Data Out
Previous Data Valid
Data Valid
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS1=OE=V
IL
, CS2=WE=V
IH
, UB or/and LB=V
IL
)
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
t
AA
t
RC
t
OH
(READ CYCLE)
1.
t
HZ
and
t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition,
t
HZ
(Max.) is less than
t
LZ
(Min.) both for a given device and from device to device
interconnection.
3. t
OE
(max) is met only when OE becomes enabled after t
AA
(max).
4. If invalid address signals shorter than min. t
RC
are continuously repeated for over 4us, the device needs a normal read timing(t
RC
) or
needs to sustain standby state for min. t
RC
at least once in every 4us.
TIMING WAVEFORM OF PAGE CYCLE(READ ONLY)
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Valid
Address
Valid
Address
Valid
Address
Valid
Address
Valid
Address
t
PC
t
PA
High Z
A21~A2
A1~A0
DQ15~DQ0
OE
t
OE
t
CO
t
AA
CS
1
CS
2
t
OHZ
t
HZ
Data Valid
High-Z
t
RC
t
OH
t
AA
t
BA
t
OE
t
OLZ
t
BLZ
t
LZ
t
OHZ
t
BHZ
t
CHZ
t
CO
Address
CS1
UB, LB
OE
Data out
t
CSHP
CS2
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| K1S6416BCC-I | 4Mx16 bit Page Mode Uni-Transistor Random Access Memory |
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|---|---|
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