參數(shù)資料
型號(hào)： K1B6416B6C
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 4Mx16 bit Synchronous Burst Uni-Transistor Random Access Memory
中文描述： 4Mx16位同步突發(fā)統(tǒng)一晶體管隨機(jī)存取存儲(chǔ)器
文件頁(yè)數(shù)： 42/46頁(yè)
文件大小： 768K
代理商： K1B6416B6C
Revision 1.0
January 2005
K1B6416B6C
- 42 -
U
t
RAM
Fig.36 ASYNCH. WRITE(Address Latch Type) to SYNCH. BURST READ TIMING WAVEFORM
[Latency=5, Burst Length=4]
(MRS=V
IH
)
1
2
3
4
5
6
7
8
9
10
11
12
13
19
20
ADV
Address
CS
LB, UB
Data out
OE
CLK
DQ0
t
CD
Valid
Latency 5
t
HZ
Valid
t
CSS(A)
T
t
OH
t
BEL
t
OEL
t
ADVS
t
ADVH
t
AS(A)
t
AH(A)
14
15
16
17
18
0
DQ1
DQ3
DQ2
WE
t
CSS(B)
Data in
High-Z
t
AS(B)
t
AH(B)
t
WP
t
BW
(SYNCHRONOUS BURST READ CYCLE)
1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
should be met.
2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
/WAIT High(tWH) : Data available(driven by Latency-1 clock)
/WAIT High-Z(tWZ) : Data don’t care(driven by CS high going edge)
3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
4. Burst Cycle Time(tBC) should not be over 2.5
μ
s.
(ADDRESS LATCH TYPE ASYNCHRONOUS WRITE CYCLE - WE controlled)
1. Clock input does not have any affect to the write operation if WE is driven to low before Read Latency-1 clock. Read Latency-1 clock
in write timing is just a reference to WE low going for proper write operation.
t
AS
Read Latency 5
t
DH
t
DW
Data Valid
Don’t Care
Don’t Care
t
AW
t
CW
TRANSITION TIMING WAVEFORM BETWEEN READ AND WRITE
t
ADV
t
WLRL
Table 40. ASYNCH. WRITE(Address Latch Type) to BURST READ AC CHARACTERISTICS
Symbol
Speed
Units
Symbol
Speed
Units
Min
Max
Min
Max
t
WLRL
1
-
clock
WAIT
High-Z
t
WH
t
WL
t
WZ
t
BC
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