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參數(shù)資料
| 型號： | IXF440 |
| 英文描述： | LAN HUB CONTROLLER |
| 中文描述： | 局域網(wǎng)集線器控制器 |
| 文件頁數(shù)： | 40/100頁 |
| 文件大?。?/td> | 1354K |
| 代理商： | IXF440 |
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IXF440 Multiport 10/100 Mbps Ethernet Controller
40
Datasheet
3.2.4
Serial Registers
The following sections describe the individual serial registers.
3.2.4.1
Serial Mode Register
The serial mode register controls the serial interface mode of work.
Bit Name
Bit Number
Bit Description
—
7:6
RESERVED
ILPK
5
Internal loopback mode.
When set, the port is disconnected from the line and all the transmitted
packets are sent back to the receive side. Packets are not transmitted
onto the line (except in the SYM mode) and packets received from the
line are rejected.
ELPK
4
External loopback mode.
When set, packets are being received and transmitted simultaneously.
This mode is usable only when the external logic is programmed to
loopback packets.
FDX
3
Full-duplex mode.
When set, packets are being received and transmitted simultaneously.
—
2
RESERVED
SCR
1
Scrambler mode.
If a SYM-100Base-TX PHY is connected, this bit must be set, and if a
SYM-100Base-FX PHY is connected, this bit must be reset. This bit is
used only if the SYP bit is set.
SYP
0
MII/SYM port mode.
This bit defines the MII/SYM port mode. If an MII PHY device is
connected, this bit must be reset. If a SYM PHY device is connected,
this bit must be set.
Access Rules
Register access
R/W
Value after reset
00H
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