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IXF440 Multiport 10/100 Mbps Ethernet Controller
iv
Datasheet
4.0
FIFO Interface Operation.................................................................................................47
4.1
FIFO Interface.....................................................................................................47
4.1.1
Byte Ordering on IX Bus .......................................................................47
4.1.2
FIFO Status Signaling............................................................................48
4.2
Packet Transmission...........................................................................................48
4.2.1
Packet Loading ......................................................................................48
4.2.2
Network Transmission............................................................................49
4.2.3
Excessive Collisions...............................................................................49
4.2.4
Late Collision..........................................................................................49
4.2.5
FIFO Underflow......................................................................................49
4.2.6
Stopping Mode on Transmission Errors.................................................50
4.2.7
Transmit Flow Diagram..........................................................................51
4.3
Packet Reception................................................................................................51
4.3.1
Packet Storing........................................................................................52
4.3.2
Header Preprocessing ...........................................................................53
4.3.3
Packet Segmentation.............................................................................53
4.3.4
Packet Abortion......................................................................................53
4.3.5
Network Reception.................................................................................54
4.3.6
Rejecting Mode on Reception Errors .....................................................54
4.3.7
Accepting Mode on Reception Errors.....................................................54
4.3.8
Receive Flow Diagram...........................................................................55
5.0
CPU Interface Operation..................................................................................................57
5.1
CPU Interface......................................................................................................57
5.2
Network Management.........................................................................................57
5.2.1
SNMP MIB Support................................................................................58
5.2.2
RMON Statistic Group Support..............................................................59
5.2.3
RMON Host Group Support ...................................................................60
6.0
Network Interface Operation............................................................................................61
6.1
Operating Modes.................................................................................................61
6.2
MII Port Interface.................................................................................................62
6.3
MAC Frame Format ............................................................................................63
6.4
MAC Transmit Operation ....................................................................................64
6.4.1
Transmit Initiation...................................................................................64
6.4.2
Initial Deferral.........................................................................................64
6.4.3
Frame Encapsulation .............................................................................64
6.4.4
Collision..................................................................................................65
6.4.5
Terminating Transmission......................................................................65
6.4.6
Backpressure .........................................................................................66
6.4.7
Flow Control...........................................................................................66
6.5
MAC Receive Operation .....................................................................................66
6.5.1
Receive Initiation....................................................................................66
6.5.2
Preamble Processing.............................................................................67
6.5.3
Frame Decapsulation.............................................................................67
6.5.4
Terminating Reception...........................................................................67
6.5.5
Flow Control...........................................................................................68
6.6
MAC Full-Duplex Operation ................................................................................68
6.7
MAC Loopback Operations.................................................................................68
6.7.1
Internal Loopback Mode.........................................................................68