參數(shù)資料
型號： IXF440
英文描述： LAN HUB CONTROLLER
中文描述： 局域網(wǎng)集線器控制器
文件頁數(shù)： 13/100頁
文件大?。?/td> 1354K
代理商： IXF440
IXF440 Multiport 10/100 Mbps Ethernet Controller
Datasheet
13
reset_l
I
General reset.
Upon reset, all the registers are reset to their default values and the FIFOs
are flushed.
FIFO Interface
clk
I
System clock.
All the FIFO data transfers are synchronized to this clock.
Transmit select.
This pin must be asserted to enable transmit FIFO write access.
Receive select.
This pin must be asserted to enable receive FIFO read access.
The following signals are driven upon assertion of rxsel_l: fdat[63:0],
fbe_l[7:0], sop, eop and rxfail.
FIFO port select/Receive FIFO port select.
In Full or Narrow, selects one of eight port FIFOs for data transfer.
In Split, selects one of eight port FIFOs for reading data, through fdat[31:0],
from the receive FIFO of the selected port.
FIFO data bus/Transmit FIFO data bus.
In Full, carries bits [63:32] of the data to be written to the transmit FIFO or
read from the receive FIFO of the selected port.
In Narrow, fdat[63:32] should be connected to pull-up resistors.
In Split, carries bits [31:0] of the data to be written to the transmit FIFO of
the selected port.
FIFO data bus/Receive FIFO data bus.
In Full, carries bits [31:0] of the data to be written to the transmit FIFO or
read from the receive FIFO of the selected port.
In Split, carries bits [31:0] of the data to be read from the receive FIFO of
the selected port.
FIFO byte enable/Transmit FIFO byte enable.
In Full:
During transmit, indicates which of the bytes driven onto fdat[63:32] contain
valid data (valid bytes need to be contiguous and at least one byte must be
valid). During receive, indicates which bytes are valid. Each fbe_l signal
relates to a different fdat byte (for example, fbe_l[4] relates to fdat[39:32] and
fbe_l[5] relates to fdat[47:40]).
In Narrow, fbe_l[7:4] should be connected to pull up resistors.
In Split, tx_fbe[3:0] are byte enables for tx_fdat[31:0] (input) that carries the
data to be written to the transmit FIFO of the selected port.
FIFO byte enable/Receive FIFO byte enable.
In Full or Narrow:
During transmit, indicates which of the bytes driven onto fdat[31:0] contain
valid data (valid bytes need to be contiguous and at least one byte must be
valid). During receive, indicates which bytes are valid. Each fbe_l signal
relates to a different fdat byte (for example, fbe_l[2] relates to fdat[23:16] and
fbe_l[0] relates to fdat[7:0]).
In Split, rx_fbe[3:0] are byte enables for rx_fdat[31:0] (output) that carries
the data to be read from the receive FIFO of the selected port.
Receive keep.
When asserted, this signal causes the last read data to be kept in the
receive FIFO. May be asserted only with rxsel_l assertion.
txsel_l
I
rxsel_l
I
fps[2:0]/rx_fps[2:0]
I
fdat[63:32]/tx_fdat[31:0]
I/O
fdat[31:0]/rx_fdat[31:0]
I/O
fbe_l[7:4]/tx_fbe[3:0]
I/O
fbe_l[3:0]/rx_fbe[3:0]
I/O
rxkep
I
Table 2. Signal Descriptions (Continued)
Signal Name
I/O
Pin Description
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