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參數(shù)資料
| 型號(hào)： | IXF440 |
| 英文描述： | LAN HUB CONTROLLER |
| 中文描述： | 局域網(wǎng)集線器控制器 |
| 文件頁(yè)數(shù)： | 10/100頁(yè) |
| 文件大小： | 1354K |
| 代理商： | IXF440 |
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IXF440 Multiport 10/100 Mbps Ethernet Controller
10
Datasheet
Table 1. IXF440 Components Description
Component
Description
Transmit FIFO
Handles the transmitted packets while taking care of retransmission in
case of collision. The transmit FIFO has direct interface to the IX Bus.
Receive FIFO
Handles the received packets and supports packet deletion in case of
errors. The receive FIFO has direct interface to the IX Bus.
Transmit MAC
Implements the IEEE 802.3 transmit MAC functions while interfacing
between the transmit FIFO and the front-end ENDEC, providing full MII
interface.
Receive MAC
Implements the IEEE 802.3 receive MAC functions while interfacing
between the front-end ENDEC through MII interface and the receive FIFO.
PCS
ENDEC implementing the 100BASE-X PCS layer, including the
100BASE-TX scrambler/descrambler function.
SNMP and RMON
Handles network statistic counters for SNMP and RMON.
Control
Handles the chip registers accessible through the CPU bus.
Clock Logic
Generates the clocks required by the chip.
JTAG
Includes the JTAG boundary scan logic.
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