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PXB4219 / PXB4220 / PXB4221
List of Tables
Page
Data Sheet
14
2000-09-04
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Generic Framer Interface (73 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
UTOPIA Interface (36 pins). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
IMA Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Clock Recovery Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
External RAM Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Test Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Not Connected Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Functions of IWE8 Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
ATM Cell Discarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Activation sequence for ATM transmit ports . . . . . . . . . . . . . . . . . . . . 49
Activation sequence for ATM receive ports . . . . . . . . . . . . . . . . . . . . 55
Definition of the CAS Signalling Conditioning Nibbles. . . . . . . . . . . . . 58
Relationship between Cell Filling and Segmentation Buffer Subblock Size
59
Table 17
Table 18
Table 19
Table 20
Cell Filling level values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Activation sequence for AAL segmentation channels. . . . . . . . . . . . . 60
Activation sequence for AAL reassembly channels . . . . . . . . . . . . . . 67
Relationship between Cell Filling and Reassembly Buffer Subblock Size
67
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Coding of Slot Type in internal configuration RAMs . . . . . . . . . . . . . . 88
RAM slot positions for ITU-T G.804 compliant ATM mapping . . . . . . 88
AAL Idle slot positions for structured CES in AAL mode . . . . . . . . . . 90
AAL Idle slot positions for structured CES with CAS in AAL mode. . . 92
Time slot Mapping in T1 Translation Mode 0. . . . . . . . . . . . . . . . . . . . 98
F-Channel Format in T1 Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Clock Recovery Interface frame format . . . . . . . . . . . . . . . . . . . . . . 114
Configuration of the Microprocessor Interface Mode via PMT and TBUS .
117
Master Clock Frequency Depending on Mode. . . . . . . . . . . . . . . . . . 121
Statistics Counters for ATM Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Statistics Counters for AAL Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Clock and Reset Interface AC Timing Characteristics . . . . . . . . . . . 252
Framer Transmit Interface Timing in FAM . . . . . . . . . . . . . . . . . . . . 255
Framer Transmit Interface Timing in GIM. . . . . . . . . . . . . . . . . . . . . 257
Framer Interface AC Timing Characteristics in SYM2 Mode . . . . . . 259
Framer Interface Timing in SYM8. . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Framer Interface Timing in EC Mode . . . . . . . . . . . . . . . . . . . . . . . . 261
Table 29
Table 30
Table 31
Table 32
Table 33
Table 34
Table 36
Table 38
Table 39
Table 40
Table 41