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參數(shù)資料
| 型號(hào)： | ISL9N316AS3ST |
| 英文描述： | TRANSISTOR | MOSFET | N-CHANNEL | 30V V(BR)DSS | 48A I(D) | TO-263AB |
| 中文描述： | 晶體管| MOSFET的| N溝道| 30V的五（巴西）直| 48A條（?。﹟對(duì)263AB |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 305K |
| 代理商： | ISL9N316AS3ST |
2002 Fairchild Semiconductor Corporation
ISL9N305ASK8T Rev A1
I
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, T
JM
, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, P
DM
, in an
application.
Therefore
the
temperature, T
A
(
o
C), and thermal resistance R
θ
JA
(
o
C/W)
must be reviewed to ensure that T
JM
is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
(
)
θ
JA
application’s
ambient
In using surface mount devices such as the SO8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power
dissipation ratings. Precise determination of P
DM
is complex
and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the R
θ
JA
for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction
temperature
or
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
power
dissipation.
Pulse
Displayed on the curve are R
θ
JA
values listed in the
Electrical Specifications table. The points were chosen to
depict the compromise between the copper board area, the
thermal resistance and ultimately the power dissipation,
P
DM
.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2. R
θ
JA
is defined as the natural log of the area
times a coefficient added to a constant. The area, in square
inches is the top copper area including the gate and source
pads.
The transient thermal impedance (Z
θ
JA
) is also effected by
varied top copper board area. Figure 22 shows the effect of
copper pad area on single pulse transient thermal
impedance. Each trace represents a copper pad area in
square inches corresponding to the descending list in the
graph. Spice and SABER thermal models are provided for
each of the listed pad areas.
Copper pad area has no perceivable effect on transient
thermal impedance for pulse widths less than 100ms. For
pulse widths less than 100ms the transient thermal
impedance is determined by the die and package.
Therefore, CTHERM1 through CTHERM5 and RTHERM1
through RTHERM5 remain constant for each of the thermal
models. A listing of the model component values is available
in Table 1.
(EQ. 1)
PDM
-----------------------------
–
=
(EQ. 2)
R
θ
JA
83.2
23.6
Area
(
)
ln
×
–
=
Figure 21. Thermal Resistance vs Mounting
Pad Area
120
160
200
240
0.1
1.0
80
0.01
R
θ
JA
= 83.2 - 23.6*
ln
(AREA)
152
o
C/W - 0.054in
2
189
o
C/W - 0.0115in
2
θ
J
(
o
C
AREA, TOP COPPER AREA (in
2
)
Figure 22. Thermal Impedance vs Mounting Pad Area
30
60
90
120
150
0
10
-1
10
0
10
1
10
2
10
3
t, RECTANGULAR PULSE DURATION (s)
Z
θ
J
,
COPPER BOARD AREA - DESCENDING ORDER
0.04 in
0.28 in
2
0.52 in
2
0.76 in
2
1.00 in
2
I
o
C
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