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IS89LV51
22
1-800-379-4774 — Integrated Silicon Solution, Inc.
ADVANCE INFORMATION
MC020-0A
10/27/98
ISSI
Table 8. Serial Port Setup
Mode
SCON
SM2Variation
0
10H
1
50H
2
90H
3
D0H
0
NA
1
70H
2
B0H
3
F0H
Single Processor
Environment
(SM2 = 0)
Multiprocessor
Environment
(SM2 = 1)
At the seventh, eighth, and ninth counter states of each bit
time, the bit detector samples the value of RXD. The value
accepted is the value that was seen in at least two of the
three samples. If the value accepted during the first bit time
is not 0, the receive circuits are reset and the unit continues
looking for another 1-to-0 transition. If the start bit proves
valid, it is shifted into the input shift register, and reception
of the rest of the frame proceeds.
As data bits come in from the right, 1s shift out to the left.
When the start bit arrives at the leftmost position in the shift
register (which in Modes 2 and 3 is a 9-bit register), it flags
the RX Control block to do one last shift, load SBUF and
RB8, and set RI. The signal to load SBUF and RB8 and to
set RI is generated if, and only if, the following conditions
are met at the time the final shift pulse is generated:
1) RI = 0, and
2) Either SM2 = 0 or the received ninth data bit = 1
If either of these conditions is not met, the received frame
is irretrievably lost, and RI is not set. If both conditions are
met, the received ninth data bit goes into RB8, and the first
eight data bits go into SBUF. One bit time later, whether the
above conditions were met or not, the unit continues
looking for a 1-to-0 transition at the RXD input.
Note that the value of the received stop bit is irrelevant to
SBUF, RB8, or RI.