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參數(shù)資料
| 型號： | IN74LV240N |
| 廠商： | INTEGRAL JOINT STOCK COMPANY |
| 英文描述： | Octal Registered Transceivers With 3-State Outputs 24-SOIC -40 to 85 |
| 中文描述： | 八路緩沖器/線路驅動，三態(tài) |
| 文件頁數(shù)： | 4/5頁 |
| 文件大?。?/td> | 44K |
| 代理商： | IN74LV240N |
IN74LV240
4
INTEGRAL
AC ELECTRICAL CHARACTERISTICS
(C
L
=50 pF, t
r
=t
f
=6.0 ns)
Test
V
CC
Guaranteed Limit
Symbol
Parameter
conditions
V
25
°
C
-40
°
C to
85
°
C
125
°
C
Unit
min max
min
max
min
max
t
PHL,
t
PLH
Propagation delay , 1An
to 1Yn, 2An to 2Yn
V
I
= 0 V or V
CC
Figure 1 and 3
1.2
2.0
*
-
-
-
100
24
15
-
-
-
125
30
19
-
-
-
150
36
23
ns
t
PHZ
t
PLZ
Propagation delay, 1OE to
1Yn, 2OE to 2Yn
V
I
= 0 V or V
CC
Figure 2 and 4
1.2
2.0
*
-
-
-
140
30
20
-
-
-
175
35
24
-
-
-
210
41
28
ns
t
PZH
t
PZL
Propagation delay, 1OE to
1Yn, 2OE to 2Yn
V
I
= 0 V or V
CC
Figure 2 and 4
1.2
2.0
*
-
-
-
140
32
20
-
-
-
175
40
25
-
-
-
210
48
30
ns
t
THL,
t
TLH
Output Transition Time,
Any Output
V
I
= 0 V or V
CC
Figure 1 and 3
1.2
2.0
*
-
-
-
60
16
10
-
-
-
75
20
13
-
-
-
90
24
15
ns
C
I
Input capacitance
3.0
-
7.0
-
7.0
-
7.0
pF
C
PD
Power dissipation
capacitance (per one
channel)
V
I
= 0 V or V
CC
-
50
-
-
-
-
pF
* V
CC
= 3.3
±
0.3 V
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
* Includes all probe and jig capacitance
* Includes all probe and jig capacitance
Figure 3. Test Circuit
Figure 4. Test Circuit
DEVICE
UNDER
TEST
OUTPUT
C
L
*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
1 k
C
L
*
TEST POINT
Connect to V
CC
when
testing t
PLZ
and t
PZL
Connect to GND
when
testing t
PHZ
and t
PZH
90%
50%
90%
50%
10%
10%
t
t
t
t
t
t
f
r
PLH
THL
TLH
PHL
V
CC
GND
1A or 2A
n
1Y or 2Y
n
t
t
t
t
PZH
PHZ
PZL
PLZ
V
V
CC
OH
GND
50%
50%
50%
1OE
2OE
or
1Y or 2Y
n
1Y or 2Y
n
GND
V
V
OL
CC
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