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參數(shù)資料
| 型號(hào)： | IN74LV240 |
| 廠商： | INTEGRAL JOINT STOCK COMPANY |
| 英文描述： | Octal Registered Transceivers With 3-State Outputs 24-SOIC -40 to 85 |
| 中文描述： | 八路緩沖器/線路驅(qū)動(dòng)，三態(tài) |
| 文件頁(yè)數(shù)： | 5/5頁(yè) |
| 文件大?。?/td> | 44K |
| 代理商： | IN74LV240 |
IN74LV240
5
INTEGRAL
CHIP PAD DIAGRAM
Location of marking (mm):
left lower corner x=1.539, y=1.433.
Chip thickness:
0.46
±
0.02 mm.
PAD LOCATION
Location (left lower corner), mm
X
0.115
0.1075
0.3215
0.76
0.9285
1.2115
1.4615
1.674
1.674
1.685
1.674
1.6795
1.674
1.0525
0.7545
0.586
0.293
0.112
0.112
0.112
Pad No
Symbol
Y
Pad size, mm
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
1OE
1A
0
2Y
3
1A
1
2Y
2
2A
2
2Y
1
2A
3
2Y
0
GND
2A
0
1Y
3
2A
1
1Y
2
2A
2
1Y
1
2A
3
1Y
0
2OE
V
CC
0.55
0.246
0.131
0.131
0.131
0.131
0.131
0.131
0.43
0.643
1.0855
1.266
1.4345
1.4345
1.4345
1.4345
1.4345
1.4345
1.1385
0.949
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
Note: Pad location is given as per metallization layer
02
(0,0)
X
Y
Chip marking
êáLV240
03
04
05
06
07
08
09
10
1.9 + 0.03
1
11
12
01
14
15
16
17
18
19
20
13
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IN74LV240DW | Octal Registered Transceivers With 3-State Outputs 24-SOIC -40 to 85 |
| IN74LV240N | Octal Registered Transceivers With 3-State Outputs 24-SOIC -40 to 85 |
| IN74LV244DW | Octal Registered Transceivers With 3-State Outputs 24-SO -40 to 85 |
| IN74LV244N | Octal Registered Transceivers With 3-State Outputs 24-PDIP -40 to 85 |
| IN74LV245 | Octal Registered Transceivers With 3-State Outputs 24-PDIP -40 to 85 |
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