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參數資料
| 型號： | IN74LV139D |
| 廠商： | INTEGRAL JOINT STOCK COMPANY |
| 英文描述： | Octal Bus Transceivers And Registers With 3-State Outputs 24-SSOP -40 to 85 |
| 中文描述： | 雙路2至4線譯碼器/解復用器;反相 |
| 文件頁數： | 6/6頁 |
| 文件大?。?/td> | 94K |
| 代理商： | IN74LV139D |
IN74LV139
6
INTEGRAL
CHIP PAD DIAGRAM
Location of marking (mm):
left lower corner x = 0.950, y = 0.130;
Thickness of chip:
0.46
±
0.02 mm
PAD LOCATION
Pad
No.
01
Ea
02
A0a
03
A1a
04
Y0a
05
Y1a
06
Y2a
07
Y3a
08
GND
09
Y3b
10
Y2b
11
Y1b
12
Y0b
13
A1b
14
A0b
15
Eb
16
Vcc
Note: Pad location is given as per passivation layer
Pad Name
X
Y
Pad size (mm)
0.1245
0.1245
0.2920
0.5480
0.7520
1.2830
1.4845
1.4840
1.4845
1.2830
0.7520
0.5480
0.2920
0.1245
0.1245
0.1245
0.4625
0.1290
0.1290
0.1290
0.1290
0.1290
0.1845
0.6770
1.1720
1.2265
1.2265
1.2265
1.2265
1.2265
0.8930
0.6650
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
0.100 x 0.100
12
10
13
14
15
16
01
09
08
07
06
05
04
03
02
11
X
Y
1.70+-0.03
1
0
Chip marking LV139
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