參數(shù)資料
型號: IMIB9688AYB
元件分類: 時(shí)鐘及定時(shí)
英文描述: LOW SKEW CLOCK DRIVER, PDSO48
文件頁數(shù): 1/8頁
文件大小: 75K
代理商: IMIB9688AYB
B9688
I
2C System Clock Buffer
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev.1.1
6/2/1999
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Page 1 of 8
Product Features
S
18 output buffer for high clock fanout applications
S
Each output can be disabled through I
2C for
reductions of EMI/power consumption
S
3.3 volts operation
S
Output frequency range 10 Mhz to 100 MHz
S
< 250ps skew between output clocks
S
48-pin SSOP package
S
Single Clock Enable pin for testability
Block Diagram
CLK[1:2]
CLK[3:4]
VDD
CLK[5:6]
CLK[7:8]
CLK[9:10]
CLK[17,18]
SDATA
SCLK
CLK[11:12]
CLK[13:14]
CLK[15:16]
VDD
Control
Logic
OE
VDD
REFIN
Product Description
The IMIB9688 is a high fanout system clock buffer.
Loads of up to 30 pF are supported. One of the chief
applications of this component is where long traces are
used to transport clocks from their generating devices
to their loads. The creation of EMI and the degradation
of waveform rise and fall times are greatly reduced by
running a single reference clock trace to this device and
then using it to regenerate the clock that drives shorter
traces. Using these devices, the EMI is therefore
minimized, and board real estate is saved.
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
NC
VDD
CLK1
CLK2
VSS
VDD
CLK3
CLK4
VDD
CLK5
CLK6
VDD
CLK7
VSS
CLK8
VSS
CLK9
VSS
VDD
SDATA
SCLOCK
VSS
CLK10
VDD
VSS
VDD
CLK13
CLK14
OE
VSS
CLK16
VDD
CLK12
VSS
VDD
CLK15
VSS
CLK17
CLK18
VDD
NC
VDD
IMIB9688
REFIN
CLK11
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