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參數(shù)資料
| 型號： | IDT74ALVCH32501BF8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ALVC/VCX/A SERIES, DUAL 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PBGA114 |
| 封裝： | LFBGA-114 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 111K |
| 代理商： | IDT74ALVCH32501BF8 |
INDUSTRIALTEMPERATURERANGE
IDT74ALVCH32501
3.3VCMOS36-BITUNIVERSALBUSTRANSCEIVERWITH3-STATEOUTPUTS
1
DECEMBER 2002
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2002 Integrated Device Technology, Inc.
DSC-4764/4
FEATURES:
0.5 MICRON CMOS Technology
Typical tSK(o) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
VCC = 2.5V ± 0.2V
CMOS power levels (0.4
μμμμμ W typ. static)
Rail-to-Rail output swing for increased noise margin
Available in 114-ball LFBGA package
FUNCTIONAL BLOCK DIAGRAM
DRIVE FEATURES:
High Output Drivers: ±24mA
Suitable for Heavy Loads
APPLICATIONS:
3.3V high speed systems
3.3V and lower voltage computing systems
IDT74ALVCH32501
3.3V CMOS 36-BIT
UNIVERSAL BUS TRANS-
CEIVER WITH 3-STATE
OUTPUTS AND BUS-HOLD
DESCRIPTION:
This 36-bit universal bus transceiver is built using advanced dual metal
CMOS technology. The ALVCH32501 combines D-type latches and Dtype
flip-flops to allow data flow in transparent latched and clocked modes. Data
flow in each direction is controlled by output-enable (OEAB and
OEBA),
latch enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For
A-to-B data flow, the device operates in transparent mode when LEAB is
high. When LEAB is low, the A data is latched if CLKAB is held at a HIGH
or low logic level. If LEAB is low, the A bus data is stored in the latch/ flip-
flop on the low-to-high transition of CLKAB. OEAB performs the output
enable function on the B port. Data flow from B port to A port is similar but
requires using
OEBA, LEBA and CLKBA. Flow-through organization of
signal pins simplifies layout. All inputs are designed with hysteresis for
improved noise margin.
This ALVCH32501 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The ALVCH32501 has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
TO 17 OTHER CHANNELS
1
OEAB
1
CLKBA
1
LEBA
1
OEBA
1
CLKAB
1
LEAB
1
A1
D
C
D
C
D
C
D
C
1
B1
A2
A3
A4
J3
K3
J4
B3
A5
TO 17 OTHER CHANNELS
2
OEAB
2
CLKBA
2
LEBA
2
OEBA
2
2
LEAB
2
A1
D
C
D
C
D
C
D
C
2
B1
L2
K2
K5
V3
W3
V4
L3
L5
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