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參數(shù)資料
| 型號： | ICS951402YGLF-T |
| 英文描述： | Programmable Timing Control Hub for P4 processor |
| 中文描述： | 可編程定時控制中心的P4處理器 |
| 文件頁數(shù)： | 12/23頁 |
| 文件大小： | 303K |
| 代理商： | ICS951402YGLF-T |
12
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
0660—05/05/05
I
2
C Table
: Output Divider Control Register
Byte 16
Pin #
Name
Control
Function
AGP divider ratio can
be configured via
these 4 bits
individually
Reserved
Reserved
Reserved
Reserved
Type
0
1
PWD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
AGP Div3
AGP Div2
AGP Div1
AGP Div0
Reserved
Reserved
Reserved
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
X
X
X
X
X
X
X
X
See Table 2: Divider
Ratio Combination
Table
-
-
-
-
-
-
-
-
I
2
C Table
: Output Divider Control Register
Byte 17
Pin #
Name
Control
Function
AGP Phase Invert
Reserved
SDRAM
Phase Invert
CPU Phase Invert
PCI divider ratio can
be configured via
these 4 bits
individually
Type
0
1
PWD
Bit 7
Bit 6
-
-
AGPINV
Reserved
RW
RW
Default
-
Inverse
-
X
X
Bit 5
-
SDINV
RW
Default
Inverse
X
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
CPUINV
PCIDiv3
PCIDiv3
PCIDiv3
PCIDiv3
RW
RW
RW
RW
RW
Default
Inverse
X
X
X
X
X
See Table 2 & 3:
Divider Ratio
Combination Table
I
2
C Table
: Group Skew Control Register
Byte 18
Pin #
Name
Control
Function
CPUT
Skew Control
SDRAM
Skew Control
Reserved
Reserved
Reserved
Reserved
Type
0
1
PWD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
CPUSkw3
CPUSkw2
SDSkw3
SDSkw2
Reserved
Reserved
Reserved
Reserved
RW
RW
RW
RW
RW
RW
RW
RW
1
0
0
1
1
1
1
1
See 2-bit Skew
Control at table 4
See 2-bit Skew
Control at table 4
-
-
-
-
-
-
-
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| ICS951411BGLF | 功能描述:IC SYSTEM CLOCK CHIP P4 56-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 專用 系列:PCI Express® (PCIe) 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
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