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參數(shù)資料
| 型號(hào)： | ICS9176-01 |
| 英文描述： | Low Skew Output Buffer |
| 中文描述： | 低偏移輸出緩沖 |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大?。?/td> | 379K |
| 代理商： | ICS9176-01 |
5
ICS9176-01
AC Characteristics
Notes:
1. Guaranteed by design and characterization. Not subject ot 100% test.
2. All skew specifications are measured with a 50W transmission line, load terminated with 50W to 1.4V.
3. Duty cycle measured at 1.4V.
4. Skew measured at 1.4V on rising edges. Loading must be equal on outputs.
PARAMETER
Input Clock Pulse Width
1
Output Rise time, 0.8 to
2.0V
1
Rise time, 20% to 80%
V
DD
Output Fall time, 2.0V to
0.8V
1
Fall time, 80% to 20%
V
DD
Output Duty cycle
1
Jitter, 1 sigma
1
Jitter, absolute
1
Input Frequency
Output Frequency
(Q outputs)
SYMBOL
CLK
W
TEST CONDITIONS
VDD=4.5V, f
CLK
=100 MHz
MIN
2.5
TYP
-
MAX
7.5
UNITS
ns
t
r
15pF load
-
0.7
1
ns
t
r
15pF load
-
1.5
2
ns
t
f
15pF load
-
0.7
1
ns
t
f
15pF load
-
1.2
2
ns
d
t
T
ls
T
abs
f
i
15pF load, Note 3
45
-
-250
20
49/51
60
±100
-
55
-
250
100
%
ps
ps
MHz
f
o
For outputs >100 MHz, use
Q/2 as feedback
Note 2, 4. Input rise time <
3ns
20
-
120
MHz
FBIN to IN skew
1
t
skew1
-500
250
0
ps
Skew between any 2 out-
puts at same frequency
1
Skew between any 1 out
put and Q/2
1
t
skew2
Note 2, 4.
-250
50
250
ps
t
skew3
Note 2, 4
-3
±0.1
3
ns
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