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參數(shù)資料
| 型號(hào)： | ICS9148GF12-T |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.240 INCH, TSSOP-48 |
| 文件頁數(shù)： | 1/18頁 |
| 文件大?。?/td> | 355K |
| 代理商： | ICS9148GF12-T |
Integrated
Circuit
Systems, Inc.
General Description
Features
ICS9148-12
0123H—03/30/04
Frequency Timing Generator for Pentium/ProTM or TransmetaTM EfficeonTM
CPU outputs are stronger drive for multiple loads
per pin (ie CPU and NB on one pin)
Generates system clocks for CPU, IOAPIC,
SDRAM, PCI, plus 14.314 MHz REF(0:1), USB,
Plus Super I/O
Supports single or dual processor systems
I
2C serial configuration interface provides output
clock disabling and other functions
MODE input pin selects optional power
management input control pins
Two fixed outputs separately selectable as 24 or
48MHz
Separate 2.5V and 3.3V supply pins
2.5V or 3.3V outputs: CPU, IOAPIC
3.3V outputs: SDRAM, PCI, REF, 48/24 MHz
CPU 3.3_2.5# logic pin to adjust output strength
No power supply sequence requirements
Uses external 14.318MHz crystal
48 pin 300 mil SSOP and 240 mil TSSOP
Output enable register
for serial port control:
1 = enable
0 = disable
ICS9148-12 is a Clock Synthesizer chip for Pentium/Pro-
based Desktop/Notebook systems or Transmeta Efficeon
Mobile systems.
Features include four strong CPU, seven PCI and eight
SDRAM clocks. Two reference outputs are available
equal to the crystal frequency. Stronger drive CPUCLK
outputs typically provide greater than 1 V/ns slew rate into
20pF loads.This device meets rise and fall requirements
with 2 loads per CPU output (ie, one clock to CPU and NB
chipset, one clock to two L2 cache inputs).
PWR_DWN# pin allows low power mode by stopping
crystal OSC and PLL stages. For optional power
management, CPU_STOP# can stop CPU (0:3) clocks
and PCI_STOP# will stop PCICLK (0:5) clocks. CPU and
IOAPIC output buffer strength controlled by CPU 3.3_2.5#
pin to match VDDL voltage.
PCICLK outputs typically provide better than 1V/ns slew
rate into 30pF loads while maintaining 50±5% duty cycle.
The REF clock outputs typically provide better than 0.5V/
ns slew rates.
The ICS9148-12 accepts a 14.318MHz reference crystal
or clock as its input and runs on a 3.3V core supply.
Functionality
VDD (1:4) 3.3V±10%, VDDL1, 2 2.5±5% or 3.3±10% 0-70
°C
Crystal (X1, X2) = 14.31818 MHz
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Pin Configuration
48-Pin SSOP & TSSOP
Block Diagram
Transmeta and Efficeon are trademarks of Transmeta Corporation.
Pentium/Pro is a trademark of Intel Corporation.
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PDF描述 |
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| ICS9148YF-111LF | 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9148YF-12 | 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9148YF-12LF | 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9148YF-37LF-T | 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| ICS9148YF-82LF | 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS9148M-46 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CPU System Clock Generator |
| ICS9148M-47 | 制造商:ICS 制造商全稱:ICS 功能描述:Pentium/ProTM System Clock Chip |
| ICS9148M-60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CPU System Clock Generator |
| ICS9148YF-10 | 制造商:ICS 制造商全稱:ICS 功能描述:Pentium/ProTM System Clock Chip |
| ICS9148YF-111 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
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