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參數(shù)資料
| 型號(hào)： | ICS1493K-17LF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 10/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK SYNTHESIZER 20-VFQFPN |
| 標(biāo)準(zhǔn)包裝： | 75 |
| 類型： | 時(shí)鐘/頻率合成器，扇出配送，擴(kuò)展頻譜時(shí)鐘發(fā)生器 |
| PLL： | 帶旁路 |
| 輸入： | 時(shí)鐘，晶體 |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:5 |
| 差分 - 輸入:輸出： | 無(wú)/無(wú) |
| 頻率 - 最大： | 48MHz |
| 除法器/乘法器： | 無(wú)/無(wú) |
| 電源電壓： | 1.7 V ~ 2 V |
| 工作溫度： | -10°C ~ 80°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 20-VFQFPN（4x4） |
| 包裝： | 管件 |
| 其它名稱： | 1493K-17LF |
ICS1493-17
CLOCK SYNTHESIZER FOR PORTABLE SYSTEMS
SYNTHESIZERS
IDT / ICS CLOCK SYNTHESIZER FOR PORTABLE SYSTEMS
7
ICS1493-17
REV A 101005
Serial Data Interface
Data Protocol
The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the
controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest
byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write
and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed
byte is encoded in the command code, as described in the following table.
The block write and block read protocol is outlined in the table below, followed by the corresponding byte write and
byte read protocol. The slave receiver address is 11010010 (D2h).
Bit
Description
7
0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0)
Byte offset for byte read or byte write operation. For block read or block write operations,
these bits should be '0000000'.
Block Write Protocol
Block Read Protocol
Bit
Description
Bit
Description
1
Start
1
Start
2:8
Slave address - 7 bits
2:8
Slave address - 7 bits
9
Write = 0
9
Write = 0
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command code — 8 bit
‘00000000’ stands for block operation
11:18
Command code - 8 bit
‘00000000’ stands for block operation
19
Acknowledge from slave
19
Acknowledge from slave
20:27
Byte count — 8 bits
20
Repeat start
28
Acknowledge from slave
21:27
Slave address — 7 bits
29:36
Data byte 0 — 8 bits
28
Read = 1
37
Acknowledge from slave
29
Acknowledge from slave
38:45
Data byte 1 — 8 bits
30:37
Byte count from slave — 8 bits
46
Acknowledge from slave
38
Acknowledge from master
....
.............................
39:46
Data byte from slave — 8 bits
....
Data byte (N-1) — 8 bits
47
Acknowledge from master
....
Acknowledge from slave
48:55
Data byte from slave — 8 bits
....
Data byte N — 8 bits
56
Acknowledge from master
....
Acknowledge from slave
....
Data byte N from slave — 8 bits
....
Stop
....
Not Acknowledge from master
....
Stop
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1493K-17LFT | 功能描述:IC CLOCK SYNTHESIZER 20-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無(wú) 頻率 - 最大:240MHz 除法器/乘法器:是/無(wú) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| ICS1494M-XXX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| ICS1494N-XXX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| ICS1522 | 制造商:ICS 制造商全稱:ICS 功能描述:User-Programmable Video Clock Generator/ Line-Locked Clock Regenerator |
| ICS1522M | 制造商:ICS 制造商全稱:ICS 功能描述:User-Programmable Video Clock Generator/ Line-Locked Clock Regenerator |
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