參數(shù)資料
型號： ICM7232BFIPL
廠商： HARRIS SEMICONDUCTOR
元件分類： 顯示驅(qū)動器
英文描述： LED AMBER DIFF 2MM RND TOP VIEW
中文描述： LIQUID CRYSTAL DISPLAY DRIVER, PDIP40
文件頁數(shù)： 5/16頁
文件大?。?/td> 103K
代理商： ICM7232BFIPL
9-23
Absolute Maximum Ratings
Thermal Information
Supply Voltage (V
DD
- V
SS
) . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.5V
Input Voltage (Note 1). . . . . . . . . . . . . . . . . . . .V
SS
- 0.3
≤
V
IN
≤
6.5
Display Voltage (Note 1). . . . . . . . . . . . . . . . . . . .0.3
≤
V
DISP
≤
+0.3
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -25
o
C to 85
o
C
Thermal Resistance (Typical, Note 2)
PDIP Package . . . . . . . . . . . . . . . . . . .
CERDIP Package . . . . . . . . . . . . . . . .
Maximum Junction Temperature
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
o
C
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300
o
C
θ
JA
(
o
C/W)
60
50
θ
JC
(
o
C/W)
N/A
12
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Due to the SCR structure inherent in these devices, connecting any display terminal or the display voltage terminal to a voltage outside
the power supply to the chip may cause destructive device latchup. The digital inputs should never be connected to a voltage less than
-0.3V below ground, but maybe connected to voltages above V
DD
but not more than 6.5V above V
SS
.
2.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
V+ = 5V +10%, V
SS
= 0V, T
A
= -25
o
C to 85
o
C, Unless Otherwise Specified
TEST CONDITIONS
PARAMETER
MIN
4.5
2
-
TYP
>4
1.6
30
MAX
5.5
-
100
UNITS
V
V
μ
A
Power Supply Voltage, V
DD
Data Retention Supply Voltage, V
DD
Logic Supply Current, I
DD
Guaranteed Retention at 2V
Current from V
DD
to Ground Excluding Display.
V
DISP
= 2V
V
DISP
Pin 2 Open
V
SS
≤
V
DISP
≤
V
DD
V
DISP
= 2V, Current from V
DD
to V
DISP
On-Chip
One of Three Identical Resistors in String
(Sample Test Only)
See Figure 5
ICM7231, Pins 30 - 35, 37 - 39, 1
ICM7232, Pins 1, 38, 39 (Note 2)
Shutdown Total Current, I
S
Display Voltage Range, V
DISP
Display Voltage Setup Current, I
DISP
Display Voltage Setup Resistor Value, R
DISP
DC Component of Display Signals
Display Frame Rate, f
DISP
Input Low Level, V
IL
Input High Level, V
IH
Input Leakage, I
ILK
Input Capacitance, C
IN
Output Low Level, V
OL
Output High Level, V
OH
Operating Temperature Range, T
OP
-
0
-
1
-
10
V
DD
30
-
1
120
0.8
-
1
-
0.4
-
+85
μ
A
V
μ
A
k
15
75
1
/
4
90
-
-
0.1
5
-
-
-
40
-
60
-
2.0
-
-
-
4.1
-25
% (V
DD
- V
DISP
)
Hz
V
V
μ
A
pF
V
V
o
C
Pin 37, ICM7232, I
OL
= 1mA
V
DD
= 4.5V, I
OH
= -500
μ
A
Industrial Range
AC Specifications
V
DD
= 5V +10% V
SS
= 0V, -25
o
C to 85
o
C
PARAMETER
PARALLEL INPUT (ICM7231)
See Figure 1
Chip Select Pulse Width, t
CS
Address/Data Setup Time, t
DS
Address/Data Hold Time, t
DH
Inter-Chip Select Time, t
ICS
SERIAL INPUT (ICM7232)
See Figures 2, 3
Data Clock Low Time, t
CL
Data Clock High Time, t
CL
Data Setup Time, t
DS
Data Hold Time, t
DH
Write Pulse Width, t
WP
Write Pulse to Clock at Initialization, t
WLL
Data Accepted Low Output Delay, t
ODL
Data Accepted High Output Delay, t
ODH
Write Delay After Last Clock, t
CWS
TEST CONDITIONS
MIN
TYP
MAX
UNITS
(Note 1)
(Note 1)
(Note 1)
(Note 1)
500
200
0
3
350
-
-20
-
-
-
-
-
ns
ns
ns
μ
s
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
350
350
200
0
500
1.5
-
-
350
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
μ
s
ns
μ
s
ns
-20
350
-
200
1.5
-
400
3
-
ICM7231, ICM7232
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