參數(shù)資料
型號(hào): IC43R16160-7TG
英文描述: 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM
中文描述: 4米× 16位× 4個(gè)銀行(256兆)DDR SDRAM內(nèi)存
文件頁(yè)數(shù): 26/56頁(yè)
文件大?。?/td> 1271K
代理商: IC43R16160-7TG
NOTE: (continued)
Row Activating: Starts with registration of an ACTIVE command and ends when
t
RCD is
met. Once
t
RCD is met, the bank will be in the “row active” state.
Read w/Auto-Precharge Enabled: Starts with registration of a READ command with AUTO PRECHARGE
enabled and ends when
t
RP has been met. Once
t
RP is met, the bank will
be in the idle state.
Write w/Auto-Precharge Enabled: Starts with registration of a WRITE command with AUTO PRECHARGE
enabled and ends when
t
RP has been met. Once
t
RP is met, the bank will
be in the idle state.
5. The following states must not be interrupted by any executable command; DESELECT or NOP commands must be
applied on each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when
t
RC is met. Once
t
RFC is met, the DDR SDRAM will be in the “all banks
idle” state.
Accessing Mode Register: Starts with registration of a MODE REGISTER SET command and ends
when
t
MRD has been met. Once
t
MTC is met, the DDR SDRAM will be in
the “all banks idle” state.
Precharging All: Starts with registration of a PRECHARGE ALL command and ends when
t
RP is met. Once
t
RP is met, all banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle and no bursts are in progress.
8. May or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ burst, regardless of bank.
10. READs or WRITEs listed in the Command/Action column include READs or WRITEs with AUTO PRECHARGE
enabled and READs or WRITEs with AUTO PRECHARGE disabled.
11. Requires appropriate DM masking.
IC4
3R16160
26
Integrated Circuit Solution Inc.
DDR001
-
0B
1
1
/
10
/
2004
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