- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄362808 > IC43R16160-7TG 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM PDF資料下載
參數(shù)資料
| 型號： | IC43R16160-7TG |
| 英文描述： | 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM |
| 中文描述： | 4米× 16位× 4個銀行（256兆）DDR SDRAM內(nèi)存 |
| 文件頁數(shù)： | 20/56頁 |
| 文件大?。?/td> | 1271K |
| 代理商： | IC43R16160-7TG |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當(dāng)前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁
Data Mask Function
The DDR SDRAM has a Data Mask function that is used in conjunction with the Write cycle, but not the
Read cycle. When the Data Mask is activated (DM high) during a Write operation, the Write is blocked (Mask
to Data Latency = 0).
When issued, the Data Mask must be referenced to both the rising and falling edges of Data Strobe.
Data Mask Timing
Burst Interruption
Read Interrupted by a Read
A Burst Read can be interrupted before completion of the burst by issuing a new Read command to any
bank. When the previous burst is interrupted, the remaining addresses are overridden with a full burst length
starting with the new address. The data from the first Read command continues to appear on the outputs until
the CAS latency from the interrupting Read command is satisfied. At this point, the data from the interrupting
Read command appears on the bus. Read commands can be issued on each rising edge of the system clock.
It is illegal to interrupt a Read with autoprecharge command with a Read command.
Read Interrupted by a Read Command Timing
(CAS Latency = Any; Burst Length = 8)
T0
T1
T2
T3
T4
T5
T6
T7
T8
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Write
CK, CK
Command
DQS
DQ
DM
T9
t
DMDQSS
t
DMDQSS
t
DMDQSH
t
DMDQSH
(CAS Latency = 2; Burst Length = 4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
Read
B
NOP
NOP
NOP
NOP
NOP
NOP
DA0 DA1 DB0 DB1
Read
A
DB2 DB3
CK, CK
Command
DQS
DQ
T9
IC4
3R16160
20
Integrated Circuit Solution Inc.
DDR001
-
0B
1
1
/
10
/
2004
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS570 | Multiplier and Zero Delay Buffer |
| ICS671M-01 | Zero Delay, Low Skew Buffer and Multipler |
| ICS671M-01T | Zero Delay, Low Skew Buffer and Multipler |
| ICS671-01 | Zero Delay, Low Skew Buffer and Multipler |
| ICS8737-11 | LOW SKEW ±1/±2 DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IC43R16160E-5TL | 制造商:Integrated Silicon Solution Inc 功能描述:256M, 2.5V, DDR, 16MX16, 200MHZ, 66 PIN |
| IC43R32400 | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) DDR SDRAM |
| IC43R32400-4B | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) DDR SDRAM |
| IC43R32400-4BG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) DDR SDRAM |
| IC43R32400-5B | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) DDR SDRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。