參數(shù)資料
型號(hào): IC43R16160-7T
英文描述: 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM
中文描述: 4米× 16位× 4個(gè)銀行(256兆)DDR SDRAM內(nèi)存
文件頁(yè)數(shù): 24/56頁(yè)
文件大小: 1271K
代理商: IC43R16160-7T
TRUTH TABLE 1 – CKE
(Notes: 1-4)
NOTE:
1. CKE
n
is the logic state of CKE at clock edge
n
; CKE
n-1
was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge
n
.
3. COMMANDn is the command registered at clock edge
n
, and ACTIONn is a result of COMMANDn.
4. All states and sequences not shown are illegal or reserved.
5. DESELECT or NOP commands should be issued on any clock edges occurring during the
t
XSR period.
A minimum of 200 clock cycles is needed before applying a read command, for the DLL to lock.
CKEn-1 CKEn
CURRENT STATE
COMMANDn
ACTIONn
NOTES
L
L
Power-Down
X
Maintain Power-Down
Self Refresh
X
Maintain Self Refresh
L
H
Power-Down
DESELECT or NOP
Exit Power-Down
Self Refresh
DESELECT or NOP
Exit Self Refresh
5
H
L
All Banks Idle
DESELECT or NOP
Precharge Power-Down Entry
Bank(s) Active
DESELECT or NOP
Active Power-Down Entry
All Banks Idle
AUTO REFRESH
Self Refresh Entry
H
H
See Truth Table 3
IC4
3R16160
24
Integrated Circuit Solution Inc.
DDR001
-
0B
1
1
/
10
/
2004
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