參數(shù)資料
型號(hào): IC43R16160-7T
英文描述: 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM
中文描述: 4米× 16位× 4個(gè)銀行(256兆)DDR SDRAM內(nèi)存
文件頁(yè)數(shù): 18/56頁(yè)
文件大小: 1271K
代理商: IC43R16160-7T
Write Interrupted by a Precharge
A Burst Write can be interrupted before completion of the burst by a Precharge command, with the only
restriction being that the interval that separates the commands be at least one clock cycle.
Write Interrupted by a Precharge Timing
Write with Auto Precharge
If A
10
is high when a Write command is issued, the Write with auto Precharge function is performed. Any
new command to the same bank should not be issued until the internal precharge is completed. The internal
precharge begins after keeping t
WR
(min.).
Write with Auto Precharge Timing
(CAS Latency = 2; Burst Length = 8)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
Write
A
NOP
Pre
A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK, CK
Command
DQS
T12
DM
D
0
D
1
D
2
D
3
DQ
Data is masked
by Precharge Command
DQS input ignored
Data is masked
by DM input
D
4
D
5
t
WR
D
6
(CAS Latency = Any; Burst Length = 4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
D
0
D
1
D
2
D
3
NOP
WAP
NOP
NOP
NOP
NOP
NOP
NOP
BA
CK, CK
Command
DQS
DQ
t
RAS
(min)
t
RP
(min)
BA
NOP
T9
T10
t
WR
(min)
Begin Autoprecharge
IC4
3R16160
18
Integrated Circuit Solution Inc.
DDR001
-
0B
1
1
/
10
/
2004
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