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| 型號： | IC43R16160-6TG |
| 英文描述： | 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM |
| 中文描述： | 4米× 16位× 4個銀行（256兆）DDR SDRAM內(nèi)存 |
| 文件頁數(shù)： | 25/56頁 |
| 文件大?。?/td> | 1271K |
| 代理商： | IC43R16160-6TG |
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TRUTH TABLE 2 – Current State Bank n - Command to Bank n
(Notes: 1-6; notes appear below and on next page)
NOTE:
1. This table applies when CKE
n-1
was HIGH and CKE
n
is HIGH (see Truth Table 2) and after
t
XSR
has been met (if the previous state was self refresh).
2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown
are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and
t
RP has been met.
Row Active: A row in the bank has been activated, and
t
RCD has been met.
No data bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with AUTO PRECHARGE disabled,
and has not yet terminated or been terminated.
Write: A WRITE burst has been initiated, with AUTO PRECHARGE disabled,
and has not yet terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank. DESELECT or NOP com-
mands,
or allowable commands to the other bank should be issued on any clock edge occurring during these states.
Allowable commands to the other bank are determined by its current state and Truth Table 3, and according to
Truth Table 4.
Precharging: Starts with registration of a PRECHARGE command and ends when
t
RP is
met. Once
t
RP is met, the bank will be in the idle state.
CURRENT STATE
/CS
/RAS
/CAS
/WE
COMMAND/ACTION
NOTES
Any
H
X
X
X
DESELECT (NOP/continue previous operation)
L
H
H
H
NO OPERATION (NOP/continue previous operation)
Idle
L
L
H
H
ACTIVE (select and activate row)
L
L
L
H
AUTO REFRESH
7
L
L
L
L
MODE REGISTER SET
7
Row Active
L
H
L
H
READ (select column and start READ burst)
10
L
H
L
L
WRITE (select column and start WRITE burst)
10
L
L
H
L
PRECHARGE (deactivate row in bank or banks)
8
Read (Auto Precharge
Disabled)
L
H
L
H
READ (select column and start new READ burst)
10
L
L
H
L
PRECHARGE (truncate READ burst, start PRECHARGE)
8
L
H
H
L
BURST TERMINATE
9
Write (Auto Precharge
Disabled)
L
H
L
H
READ (select column and start READ burst)
10, 11
L
H
L
L
WRITE (select column and start new WRITE burst)
10
L
L
H
L
PRECHARGE (truncate WRITE burst, start PRECHARGE)
8, 11
IC4
3R16160
Integrated Circuit Solution Inc.
DDR001-0B
1
1
/
10
/
2004
25
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| IC43R16160-7T | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM |
| IC43R16160-7TG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM |
| IC43R16160E-5TL | 制造商:Integrated Silicon Solution Inc 功能描述:256M, 2.5V, DDR, 16MX16, 200MHZ, 66 PIN |
| IC43R32400 | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) DDR SDRAM |
| IC43R32400-4B | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) DDR SDRAM |
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