參數(shù)資料
型號(hào)： IC43R16160-5TG
英文描述： 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM
中文描述： 4米× 16位× 4個(gè)銀行（256兆）DDR SDRAM內(nèi)存
文件頁(yè)數(shù)： 22/56頁(yè)
文件大?。?/td> 1271K
代理商： IC43R16160-5TG
Write Interrupted by a Read
A Burst Write can be interrupted by a Read command to any bank. If a burst write operation is interrupted
prior to the end of the burst operation, then the last two pieces of input data prior to the Read command must
be masked off with the data mask (DM) input pin to prevent invalid data from being written into the memory
array. Any data that is present on the DQ pins coincident with or following the Read command will be masked
off by the Read command and will not be written to the array. The memory controller must give up control of
both the DQ bus and the DQS bus at least one clock cycle before the read data appears on the outputs in
order to avoid contention. In order to avoid data contention within the device, a delay is required (t
CDLR
) from
the last valid data input before a Read command can be issued to the device. It is illegal to interrupt a Write
with autoprecharge command with a Read command.
Write Interrupted by a Read Command Timing
Auto Refresh
The Auto Refresh command is issued by having CS, RAS, and CAS held low with CKE and WE high at the
rising edge of the clock. All banks must be precharged and idle for a t
RP
(min) before the Auto Refresh com-
mand is applied. No control of the address pins is required once this cycle has started because of the internal
address counter. When the Auto Refresh cycle has completed, all banks will be in the idle state. A delay be-
tween the Auto Refresh command and the next Activate command or subsequent Auto Refresh command
must be greater than or equal to the t
RFC
(min). Commands may not be issued to the device once an Auto
Refresh cycle has begun. CS input must remain high during the refresh period or NOP commands must be
registered on each rising edge of the CK input until the refresh period is satisfied.
Auto Refresh Timing
(CAS Latency = 2; Burst Length = 8)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
Write
NOP
Read
NOP
t
WTR
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK, CK
Command
DQS
T12
DM
D
2
D
3
D
4
D
5
D
0
D
2
D
3
D
4
D
5
D
6
D
1
D
7
DQ
Data is masked
by Read command
DQS input ignored
Data is masked
by DM input
D
0
D
1
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
NOP
NOP
NOP
CK, CK
Command
CKE
T11
Auto Ref
ANY
High
Pre All
t
RFC
t
RP
IC4
3R16160
22
Integrated Circuit Solution Inc.
DDR001
-
0B
1
1
/
10
/
2004
相關(guān)PDF資料
PDF描述
IC43R16160-6T 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM
IC43R16160-6TG 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM
IC43R16160-7T 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM
IC43R16160-7TG 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM
ICS570 Multiplier and Zero Delay Buffer
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IC43R16160-6T 制造商:ICSI 制造商全稱(chēng):Integrated Circuit Solution Inc 功能描述:4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM
IC43R16160-6TG 制造商:ICSI 制造商全稱(chēng):Integrated Circuit Solution Inc 功能描述:4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM
IC43R16160-7T 制造商:ICSI 制造商全稱(chēng):Integrated Circuit Solution Inc 功能描述:4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM
IC43R16160-7TG 制造商:ICSI 制造商全稱(chēng):Integrated Circuit Solution Inc 功能描述:4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM
IC43R16160E-5TL 制造商:Integrated Silicon Solution Inc 功能描述:256M, 2.5V, DDR, 16MX16, 200MHZ, 66 PIN
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