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參數(shù)資料
| 型號： | IC42S16101-7T |
| 英文描述： | 512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| 中文描述： | 為512k × 16位× 2銀行（16兆）內(nèi)存 |
| 文件頁數(shù)： | 35/78頁 |
| 文件大小： | 786K |
| 代理商： | IC42S16101-7T |
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IC42S16101
Integrated Circuit Solution Inc.
DR025-0F 01/17/2005
35
CAS
latency = 2, burst length = 4
READ 0
COMMAND
CKE
I/O
CLK
D
OUT
0
D
OUT
1
D
OUT
2
D
OUT
3
READ (BANK 0)
CLOCK SUSPEND
Bank Active Command Interval
When the selected bank is precharged, the period trp has
elapsed and the bank has entered the idle state, the bank
can be activated by executing the active command. If the
other bank is in the idle state at that time, the active
command can be executed for that bank after the period
t
RRD
has elapsed. At that point both banks will be in the
active state. When a bank active command has been
executed, a precharge command must be executed for
that bank within the ACT to PRE command period (t
RAS
max). Also note that a precharge command cannot be
executed for an active bank before t
RAS
(min) has elapsed.
After a bank active command has been executed and the
trcd period has elapsed, read write (including auto-
precharge) commands can be executed for that bank.
ACT 0
ACT 1
COMMAND
CLK
BANK ACTIVE (BANK 0)
BANK ACTIVE (BANK 1)
t
RRD
ACT 0
READ 0
COMMAND
CLK
BANK ACTIVE (BANK 0)
BANK ACTIVE (BANK 0)
t
RCD
Clock Suspend
When the CKE pin is dropped from HIGH to LOW during
a read or write cycle, the IS42S16101 enters clock suspend
mode on the next CLK rising edge. This command reduces
the device power dissipation by stopping the device
internal clock. Clock suspend mode continues as long as
the CKE pin remains low. In this state, all inputs other than
CKE pin are invalid and no other commands can be
executed. Also, the device internal states are maintained.
When the CKE pin goes from LOW to HIGH clock suspend
mode is terminated on the next CLK rising edge and
device operation resumes.
The next command cannot be executed until the recovery
period (t
CKA
) has elapsed.
Since this command differs from the self-refresh command
described previously in that the refresh operation is not
performed automatically internally, the refresh operation
must be performed within the refresh period (tref). Thus
the maximum time that clock suspend mode can be held
is just under the refresh cycle time.
CAS
latency = 3
相關PDF資料 |
PDF描述 |
|---|---|
| IC42S16101-7TG | 512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| IC42S16101-7TI | 512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| IC42S16101-7TIG | 512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| IC42S16102 | 512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| IC42S16102-5BG | 512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IC42S16101-7TG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| IC42S16101-7TI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| IC42S16101-7TIG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| IC42S16102 | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| IC42S16102-5BG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
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