- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄362807 > IC42S16101-5TI 512K x 16 Bit x 2 Banks (16-MBIT) SDRAM PDF資料下載
參數(shù)資料
| 型號： | IC42S16101-5TI |
| 英文描述： | 512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| 中文描述： | 為512k × 16位× 2銀行（16兆）內(nèi)存 |
| 文件頁數(shù)： | 7/78頁 |
| 文件大小： | 786K |
| 代理商： | IC42S16101-5TI |
第1頁第2頁第3頁第4頁第5頁第6頁當(dāng)前第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁
IC42S16101
Integrated Circuit Solution Inc.
DR025-0F 01/17/2005
7
Notes:
1.
When power is first applied, memory operation should be started 100 μs after Vcc and VccQ reach their stipulated
voltages. Also note that the power-on sequence must be executed before starting memory operation.
Measured with t
T
= 1 ns.
The reference level is 1.4 V when measuring input signal timing. Rise and fall times are measured between V
IH
(min.) and
V
IL
(max.).
Access time is measured at 1.4V with the load shown in the figure below.
The time t
HZ
(max.) is defined as the time required for the output voltage to transition by ± 200 mV from V
OH
(min.) or V
OL
(max.) when the output is in the high impedance state.
2.
3.
4.
5.
AC CHARACTERISTICS
(1,2,3)
-5
-6
-7
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max
Units
t
CK
3
t
CK
2
t
AC
3
t
AC
2
t
CHI
t
CL
t
OH
t
LZ
t
HZ
3
t
HZ
2
t
DS
t
DH
t
AS
t
AH
t
CKS
t
CKH
t
CKA
t
CS
t
CH
t
RC
t
RAS
t
RP
t
RCD
t
RRD
t
DPL
Clock Cycle Time
CAS
Latency = 3
CAS
Latency = 2
CAS
Latency = 3
CAS
Latency = 2
5
7
—
—
2
2
2
0
—
—
2
1
2
1
2
1
—
—
4.5
5
—
—
—
—
4.5
5
—
—
—
—
—
—
—
—
—
—
6
8
—
—
2
2
2
0
—
—
2
1
2
1
2
1
—
—
5.5
6
—
—
—
—
5.5
6
—
—
—
—
—
—
—
—
—
—
7
—
—
6
6
—
—
—
—
6
6
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8.6
—
—
2.5
2.5
2
0
—
—
2
1
2
1
2
1
Access Time From CLK
(4)
CLK HIGH Level Width
CLK LOW Level Width
Output Data Hold Time
Output LOW Impedance Time
Output HIGH Impedance Time
(5)
CAS
Latency = 3
CAS
Latency = 2
Input Data Setup Time
Input Data Hold Time
Address Setup Time
Address Hold Time
CKE Setup Time
CKE Hold Time
CKE to CLK Recovery Delay Time
Command Setup Time (
CS
,
RAS
,
CAS
,
WE
, DQM)
Command Hold Time (
CS
,
RAS
,
CAS
,
WE
, DQM)
Command Period (REF to REF / ACT to ACT)
Command Period (ACT to PRE)
Command Period (PRE to ACT)
Active Command To Read / Write Command Delay Time
Command Period (ACT [0] to ACT[1])
Input Data To Precharge
Command Delay time
Input Data To Active / Refresh
Command Delay time (During Auto-Precharge)
t
T
Transition Time
t
REF
Refresh Cycle Time (4096)
1CLK+3
2
1
50
30
15
15
10
2CLK
1CLK+3
2
1
60
36
18
18
12
2CLK
1CLK+3
2
1
70
42
21
21
14
2CLK
100,000
—
—
—
—
100,000
—
—
—
—
100,000
—
—
—
—
t
DAL
2CLK+t
RP
—
2CLK+t
RP
—
2CLK+t
RP
—
ns
1
—
10
64
1
—
10
64
1
—
10
64
ns
ms
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IC42S16101-5TIG | 512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| IC42S16101-6BG | 512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| IC42S16101-6BIG | 512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| IC42S16101-6T | 512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| IC42S16101-6TG | 512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IC42S16101-5TIG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| IC42S16101-6BG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| IC42S16101-6BIG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| IC42S16101-6T | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| IC42S16101-6TG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。