參數(shù)資料
型號(hào)： M37906M4H-XXXSP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PDIP42
封裝： 0.600 INCH, 1.78 MM PITCH, PLASTIC, SDIP-42
文件頁(yè)數(shù)： 41/101頁(yè)
文件大?。?/td> 766K
代理商： M37906M4H-XXXSP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Som
e param
etric
lim
its are
subject
to change.
44
M37906M4C-XXXFP, M37906M4C-XXXSP, M37906M4H-XXXFP
M37906M4H-XXXSP, M37906M6C-XXXFP, M37906M6C-XXXSP
M37906M8C-XXXFP, M37906M8C-XXXSP
16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PULSE OUTPUT PORT MODE
Figure 48 shows the block diagram in the pulse output port mode.
This mode has a 6-bit pulse output port. The waveform output select
bits (bits 0 to 2) of waveform output mode register (address A616)
select use of pulse output port. The 6-bit pulse output port can also
be divided into 4 bits and 2 bits with the pulse output mode select bit
(bit 3) of waveform output mode register (address A616); each of
them can be individually controlled.
Set timers A3 and A0 to the timer mode because they are used in the
pulse output port mode. Figure 50 shows the bit configuration of
timer A3 and A0 mode registers in the pulse output port mode.
Timers A3 and A0 start count when setting the corresponding timer
count start bit to “1”, and they stop it when clearing that bit to “0”.
Fig. 48 Block diagram in pulse output port mode
Each bit using timer A0 as a trigger can also be controlled by an in-
put trigger from pin RTPTRG0. This control is selected by the pulse
output trigger select bits of the three-phase output data register 0
(bits 7 and 6 at address A816). Also, this externally-input trigger can
be selected from the following three types: falling edges, rising
edges, and falling and rising edges.
The reversed content of the pulse output data bit can be output to
each pulse output port by the pulse output polarity select bit of the
three-phase output data register 1 (bit 3 at address A916). When the
pulse output polarity select bit = “0”, the content of the pulse output
data bit is output as it is; when the pulse output polarity select bit =
“1”, the reversed content is output.
Bits 0 through 3 of three-
phase output data register 0
(address A816)
Pulse width modulation
output of timer A1
Bits 4, 5 of three-phase output data register 0
(address A816)
or
Bits 4, 5 of three-phase output data register 1
(address A916)
Data
bus
(even-numbered)
b0
b1
b2
b0
b1
b2
b3
b4
b5
Pulse output mode
select bit
(bit 3 at address A616)
Pulse width modulation timer select bits
(bits 5, 4 at address A616)
RTP10
RTP11
Pulse output polarity
select bit
(bit 3 at address A916)
RTP03
D Q
Pulse width modulation enable bits
0 through 2
(bits 0 through 2 at address A916)
D Q
Data
bus
(odd-numbered)
Waveform output
control bit 0
(bit 6 at address A616)
Reset
Waveform output control bit 1
(bit 7 at address A616)
Reset
Pulse width modulation
output of timer A2
Pulse width modulation
output of timer A4
T
D Q
RTP01
RTP02
D Q
R
T
D Q
R
RTP00
T
D Q
Pulse width
modulation
circuit
P6OUTCUT
Timer A0
Pulse output triggger select bits
(bits 7, 6 at address A816)
RTPTRG0
Timer A3
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參數(shù)描述
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