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參數(shù)資料
| 型號： | IA186ES |
| 廠商： | Innovasic Semiconductor |
| 英文描述： | PCI FAST ETHERNET LAN CONTROLLER |
| 中文描述： | PCI快速以太網(wǎng)LAN控制器 |
| 文件頁數(shù)： | 6/19頁 |
| 文件大?。?/td> | 94K |
| 代理商： | IA186ES |
IA21140AF Preliminary
Data Sheet
PCI FAST ETHERNET LAN CONTROLLER
NAME
Type
irdy_n
I/O
When the IA21140AF is the bus master, this signal is asserted during write
operations indicating valid data is present on the 32-bit ad bus. It is asserted
during read operations to indicate the master is ready to accept data. It is
asserted during a write to indicate that valid data is on the AD lines. A data
phase is completed on any rising edge of the clock when both irdy_n and
trdy_n are asserted. Wait cycles are inserted until both these signals are
asserted together.
mii_clsn
I
When an external physical layer protocol (PHY) device detects a collision, it
asserts this signal.
Carrier sense
mii_crs
mii_dv
I
An external PHY sets this bit when receive data is on the mii_sym_rxd lines
and is cleared at the end of the packet. This signal is synchronized with
mii_sym_rclk.
mii_err
I
When a data decoding error is detected by an external PHY device, this pin
gets set. It is synchronized to mii_sym_rclk and can be set for a minimum of
one receive clock. It sets the cyclic redundancy check (CRC) error bit in the
receive descriptor (RDES0) when it is set during a packet reception.
Copyright
2001
innov
ASIC
The End of Obsolescence
ENG210010110-00
www.innovasic.com
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Description
I
The PHY sets this bit when the media is active.
mii_mdc
O
Goes to the PHY devices as timing reference for the transfer of information
on the mii_mdio signal.
Transfers control information and status between the IA21140AF and PHY.
Set when the MII/SYM port is selected. Cleared when the SRL port is
selected.
This clock, recovered by the PHY, supports either the 25 MHz or 2.5 MHz
receive clock.
When MII mode is selected, these four parallel data lines receive data that is
driven by external PHY that attached the media. Synchronized to the
mii_sym_rclk signal.
This 25 MHz or 2.5 MHz transmit clock is supplied by the external physical
layer medium dependent device (PMD) and must always be active.
These four parallel transmit data lines are synchronized and latched by the
external PHY on the rising edge of the mii_sym_tclk signal.
This signal indicates a transmit to an external PHY device. It reflects the
transmit activity of the MAC sublayer when in the PCS mode (CSR6[23]).
No connection pins
Even parity bit for the 32-bit ad bus and the 4-bit c_be_n lines. It is driven by
the master for address and write data phases and driven by the target for
read data phases.
Timing of the PCI related functions is based on this DC to 33 MHz clock. All
bus signals except int_n and rst_n are sampled on the rising edge of this
clock.
Used for reporting data parity errors during all PCI transactions except a
special cycle.
Set when a received packet passes address recognition.
Request to the bus arbiter for the IA21140AF to use the bus.
When asserted for at least 10 PCI clock cycles, the IA21140AF is reset to its
initial state. PCI output pins are tristated and all PCI O/D signals are left
floating.
Supplied by an external PMD device.
mii_mdio
mii_srl
I/O
O
mii_sym_rclk
I
mii_sym_rxd[3:0]
I
mii_sym_tclk
I
mii_sym_txd[3:0]
O
mii_txen
O
Nc
Par
O
I/O
pci_clk
I
perr_n
I/O
rcv_match
req_n
rst_n
O
O
I
sd
I
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