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參數(shù)資料
| 型號： | HY62SF16804B-SFI |
| 廠商： | Hynix Semiconductor Inc. |
| 元件分類： | DRAM |
| 英文描述： | 512K x16 bit 1.8V Super Low Power Full CMOS slow SRAM |
| 中文描述： | 為512k x16位1.8V的超低功耗SRAM的速度進(jìn)行全面的CMOS |
| 文件頁數(shù)： | 8/10頁 |
| 文件大小： | 311K |
| 代理商： | HY62SF16804B-SFI |
HY62SF16804B
Notes:
1. A write occurs during the overlap of a low / WE, a low /CS1 and low /UB and /or /LB
2. tWR is measured from the earlier of /CS, /LB, /UB, or /WE going high to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the
output must not be applied.
4. If the /CS, /LB and /UB low transition occur simultaneously with the /WE low transition or after the
/WE transition, outputs remain in a high impedance state.
5. Q(data out) is the same phase with the write data of this write cycle.
6. Q(data out) is the read data of the next address.
7. Transition is measured +200mV from steady state.
This parameter is sampled and not 100% tested.
8. /CS in high for the standby, low for active
/UB and /LB in high for the standby, low for active
DATA RETENTION ELECTRIC CHARACTERISTIC
T
A
= 0
°
C to 70
°
C / -40
°
C to 85
°
C
Symbol
Parameter
Test Condition
/CS > Vcc - 0.2V or
/UB=/LB > Vcc-0.2V,
V
IN
> Vcc-0.2V or
V
IN
< Vss+0.2V
Vcc=1.5V, /CS > Vcc - 0.2V or LL
/UB=/LB > Vcc-0.2V,
V
IN
> Vcc-0.2V or
V
IN
< Vss+0.2V
Chip Deselect to Data
Retention Time
tR
Operating Recovery Time
Notes:
1. Typical values are under the condition of T
A
= 25
°
C .
2. tRC is read cycle time.
DATA RETENTION TIMING DIAGRAM
VCC
DATA RETENTION MODE
Rev.00/May. 2001
7
Min
Typ
Max
Unit
V
DR
Vcc for Data Retention
1.2
-
2.3
V
-
1
12
uA
I
CCDR
Data Retention Current
SL
-
-
8
uA
tCDR
0
-
-
ns
See Data Retention Timing Diagram
tRC
(2)
-
-
ns
/CS or
/UB & /LB
VDR
/CS>Vcc-0.2V or
/UB=/LB > Vcc-0.2V
tCDR
tR
Vss
1.65V
VIH
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY62VT08081E-DGI | 32Kx8bit CMOS SRAM |
| HY62VT08081E-DTC | 32Kx8bit CMOS SRAM |
| HY62VT08081E-DTE | 32Kx8bit CMOS SRAM |
| HY62VT08081E-DTI | 32Kx8bit CMOS SRAM |
| HY62UT08081E-DGC | 32Kx8bit CMOS SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY62SF16806A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16|1.8V|70/85/100|Super Low Power Slow SRAM - 8M |
| HY62SF16806A-C | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Kx16bit full CMOS SRAM |
| HY62SF16806A-DM10C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SRAM |
| HY62SF16806A-DM10I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SRAM |
| HY62SF16806A-DM70C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SRAM |
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