參數(shù)資料
型號(hào): HY5PS1G431CLFP
廠商: Hynix Semiconductor Inc.
英文描述: 1Gb DDR2 SDRAM
中文描述: 1G DDR2內(nèi)存
文件頁數(shù): 12/37頁
文件大小: 539K
代理商: HY5PS1G431CLFP
Rev. 0.2 / Dec 2006
12
HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
3.2 DC & AC Logic Input Levels
3.2.1 Input DC Logic Level
3.2.2 Input AC Logic Level
3.2.3 AC Input Test Conditions
Note:
1. Input waveform timing is referenced to the input signal crossing through the V
REF
level applied to the device
under test.
2. The input signal minimum slew rate is to be maintained over the range from V
REF
to V
IH(ac)
min for rising
edges and the range from V
REF
to V
IL(ac)
max for falling edges as shown in the figure below.
3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions
and VIH(ac) to VIL(ac) on the negative transitions.
< Figure : AC Input Test Signal Waveform>
Symbol
V
IH
(dc)
V
IL
(dc)
Parameter
Min.
Max.
Units
V
Notes
dc input logic high
VREF + 0.125
VDDQ + 0.3
dc input logic low
- 0.3
VREF - 0.125
V
Symbol
Parameter
DDR2 400,533
DDR2 667,800
Units
Notes
Min.
Max.
-
Min.
Max.
-
V
IH
(ac)
V
IL
(ac)
ac input logic high
VREF + 0.250
VREF + 0.200
V
ac input logic low
-
VREF - 0.250
-
VREF - 0.200
V
Symbol
V
REF
V
SWING(MAX)
SLEW
Condition
Value
0.5 * V
DDQ
1.0
Units
V
Notes
1
Input reference voltage
Input signal maximum peak to peak swing
V
1
Input signal minimum slew rate
1.0
V/ns
2, 3
V
DDQ
V
IH(ac)
min
V
IH(dc)
min
V
REF
V
IL(dc)
max
V
IL(ac)
max
V
SS
V
SWING(MAX)
delta TR
delta TF
Rising Slew =
delta TR
V
IH(ac)
min - V
REF
V
REF
- V
IL(ac)
max
delta TF
Falling Slew =
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