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參數(shù)資料
| 型號： | HY5DU56822DT |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | 256Mb DDR SDRAM |
| 中文描述： | 256Mb的DDR SDRAM內(nèi)存 |
| 文件頁數(shù)： | 5/29頁 |
| 文件大?。?/td> | 236K |
| 代理商： | HY5DU56822DT |
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Rev. 1.0 /Oct. 2004
5
HY5DU56422D(L)T
HY5DU56822D(L)T
HY5DU561622D(L)T
PIN DESCRIPTION
PIN
TYPE
DESCRIPTION
CK, /CK
Input
Clock: CK and /CK are differential clock inputs. All address and control input sig-
nals are sampled on the crossing of the positive edge of CK and negative edge of
/CK. Output (read) data is referenced to the crossings of CK and /CK (both direc-
tions of crossing).
CKE
Input
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock sig-
nals, and device input buffers and output drivers. Taking CKE LOW provides PRE-
CHARGE POWER DOWN and SELF REFRESH operation (all banks idle), or ACTIVE
POWER DOWN (row ACTIVE in any bank). CKE is synchronous for POWER
DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for
SELF REFRESH exit, and for output disable. CKE must be maintained high
throughout READ and WRITE accesses. Input buffers, excluding CK, /CK and
CKE are disabled during POWER DOWN. Input buffers, excluding CKE are dis-
abled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS
LOW level after VDD is applied.
/CS
Input
Chip Select: Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All
commands are masked when CS is registered high. CS provides for external bank
selection on systems with multiple banks. CS is considered part of the command
code.
BA0, BA1
Input
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write
or PRECHARGE command is being applied.
A0 ~ A12
Input
Address Inputs: Provide the row address for ACTIVE commands, and the column
address and AUTO PRECHARGE bit for READ/WRITE commands, to select one
location out of the memory array in the respective bank. A10 is sampled during a
precharge command to determine whether the PRECHARGE applies to one bank
(A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the
bank is selected by BA0, BA1. The address inputs also provide the op code dur-
ing a MODE REGISTER SET command. BA0 and BA1 define which mode register
is loaded during the MODE REGISTER SET command (MRS or EMRS).
/RAS, /CAS, /
WE
Input
Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command
being entered.
DM
(LDM,UDM)
Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked
when DM is sampled HIGH along with that input data during a WRITE access.
DM is sampled on both edges of DQS. Although DM pins are input only, the DM
loading matches the DQ and DQS loading. For the x16, LDM corresponds to the
data on DQ0-Q7; UDM corresponds to the data on DQ8-Q15.
DQS
(LDQS,UDQS)
I/O
Data Strobe: Output with read data, input with write data. Edge aligned with
read data, centered in write data. Used to capture write data. For the x16, LDQS
corresponds to the data on DQ0-Q7; UDQS corresponds to the data on DQ8-
Q15.
DQ
I/O
Data input / output pin: Data bus
VDD/VSS
Supply
Power supply for internal circuits and input buffers.
VDDQ/VSSQ
Supply
Power supply for output buffers for noise immunity.
VREF
Supply
Reference voltage for inputs for SSTL interface.
NC
NC
No connection.
相關(guān)PDF資料 |
PDF描述 |
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| HY5DU56422BT-D4 | 256M-P DDR SDRAM |
| HY5DU56822BT-D | 256M-P DDR SDRAM |
| HY5DU56422CT-D | 256M-P DDR SDRAM |
| HY5DU561622CT-D4 | 256M-P DDR SDRAM |
| HY5DU561622CT-D43 | 256M-P DDR SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY5DU56822DTP | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU56822DTP-H | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU56822DTP-J | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU56822DTP-K | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU56822DTP-L | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
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