參數資料
型號: HY5DU56822BT-D
廠商: Hynix Semiconductor Inc.
英文描述: 256M-P DDR SDRAM
中文描述: 256M磷DDR SDRAM內存
文件頁數: 18/32頁
文件大?。?/td> 233K
代理商: HY5DU56822BT-D
Rev. 0.4 / Aug. 2003 18
HY5DU56422BT-D4/ D43
HY5DU56822BT-D4/ D43
MODE REGISTER SET (MRS)
The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length,
burst type, test mode, DLL reset. The mode register is programed via MRS command. This command is issued by the
low signals of /RAS, /CAS, /CS, /WE and BA0. This command can be issued only when all banks are in idle state and
CKE must be high at least one cycle before the Mode Register Set Command can be issued. Two cycles are required to
write the data in mode register. During the MRS cycle, any command cannot be issued. Once mode register field is
determined, the information will be held until resetted by another MRS command.
BA1
BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
RFU*
DR
TM
CAS Latency
BT
Burst Length
A2
A1
A0
Burst Length
Sequential
Interleave
0
0
0
Reserved
Reserved
0
0
1
2
2
0
1
0
4
4
0
1
1
8
8
1
0
0
Reserved
Reserved
1
0
1
Reserved
Reserved
1
1
0
Reserved
Reserved
1
1
1
Reserved
Reserved
A3
Burst Type
0
Sequential
1
Interleave
A6
A5
A4
CAS Latency
0
0
0
Reserved
0
0
1
Reserved
0
1
0
2
0
1
1
3
1
0
0
Reserved
1
0
1
1.5
1
1
0
2.5
1
1
1
Reserved
A7
Test Mode
0
Normal
1
Test
A8
DLL Reset
0
No
1
Yes
BA0
MRS Type
0
MRS
1
EMRS
* All bits in RFU address fields must be programmed to Zero, all reserved states not defined in this specification
should not be used, as unknown operation or incompatibility with future versions may result.
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