參數(shù)資料
型號： HY5DU56422DLT
廠商： Hynix Semiconductor Inc.
英文描述： 256Mb DDR SDRAM
中文描述： 256Mb的DDR SDRAM內(nèi)存
文件頁數(shù)： 9/29頁
文件大?。?/td> 236K
代理商： HY5DU56422DLT
Rev. 1.0 /Oct. 2004
9
HY5DU56422D(L)T
HY5DU56822D(L)T
HY5DU561622D(L)T
SIMPLIFIED COMMAND TRUTH TABLE
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
ADDR
A10/
AP
BA
Extended Mode Register Set
1,2
Mode Register Set
1,2
Device Deselect
1
No Operation
1
Bank Active
1
Read
1
Read with Autoprecharge
1,3
Write
1
Write with Autoprecharge
1,4
Precharge All Banks
1,5
Precharge selected Bank
1
Read Burst Stop
1
Auto Refresh
1
H
X
L
L
L
L
OP code
H
X
L
L
L
L
OP code
H
X
H
X
X
X
X
L
H
H
H
H
X
L
L
H
H
RA
V
H
X
L
H
L
H
CA
L
V
H
H
X
L
H
L
L
CA
L
V
H
H
X
L
L
H
L
X
H
X
L
V
H
X
L
H
H
L
X
H
H
L
L
L
H
X
Self Refresh
1
Entry
H
L
L
H
L
H
L
H
L
H
L
L
X
H
X
H
X
H
X
V
L
X
H
X
H
X
H
X
V
H
X
H
X
H
X
H
X
V
X
Exit
L
H
Precharge Power
Down Mode
1
Entry
H
L
X
Exit
L
H
Active Power Down
Mode
1
Entry
H
L
X
Exit
L
H
X
Note:
1. LDM/UDM states are Don’t Care. Refer to below Write Mask Truth Table.
2. OP Code(Operand Code) consists of A0~A12 and BA0~BA1 used for Mode Register setting during Extended MRS or
MRS. Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be
issued after tRP period from Precharge command.
3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no com-
mand presented to activated bank until CK(n+BL/2+tRP).
4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no com-
mand presented to activated bank until CK(n+BL/2+1+tWR+tRP). Write Recovery Time (tWR) is needed to
guarantee that the last data has been completely written.
5. If A10/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be
precharged.
*For more information about Truth Table, refer to “Device Operation” section in Hynix website.
( H=Logic High Level, L=Logic Low Level, X=Don’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No)
相關(guān)PDF資料
PDF描述
HY5DU56422DT 256Mb DDR SDRAM
HY5DU56822DLT 256Mb DDR SDRAM
HY5DU56822DT 256Mb DDR SDRAM
HY5DU56422BT-D4 256M-P DDR SDRAM
HY5DU56822BT-D 256M-P DDR SDRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HY5DU56422DLTP 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM)
HY5DU56422DLTP-H 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM)
HY5DU56422DLTP-J 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM)
HY5DU56422DLTP-K 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM)
HY5DU56422DLTP-L 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM)
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