- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384467 > HY5DU56422DLT (Hynix Semiconductor Inc.) 256Mb DDR SDRAM PDF資料下載
參數(shù)資料
| 型號： | HY5DU56422DLT |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | 256Mb DDR SDRAM |
| 中文描述： | 256Mb的DDR SDRAM內(nèi)存 |
| 文件頁數(shù)： | 3/29頁 |
| 文件大?。?/td> | 236K |
| 代理商： | HY5DU56422DLT |
第1頁第2頁當(dāng)前第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁
Rev. 1.0 /Oct. 2004
3
HY5DU56422D(L)T
HY5DU56822D(L)T
HY5DU561622D(L)T
DESCRIPTION
The HY5DU56422D(L)T, HY5DU56822D(L)T and HY5DU561622D(L)T are a 268,435,456-bit CMOS Double Data
Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density
and high bandwidth.
This Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
VDD, VDDQ = 2.5V +/- 0.2V for DDR200, 266, 333
VDD, VDDQ = 2.6V +/- 0.1V for DDR400
All inputs and outputs are compatible with SSTL_2
interface
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous - data transaction aligned to
bidirectional data strobe (DQS)
x16 device has two bytewide data strobes (UDQS,
LDQS) per each x8 I/O
Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
On chip DLL align DQ and DQS transition with CK
transition
DM mask write data-in at the both rising and falling
edges of the data strobe
All addresses and control inputs except data, data
strobes and data masks latched on the rising edges
of the clock
Programmable CAS latency 2/2.5 (DDR200, 266,
333) and 3 (DDR400) supported
Programmable burst length 2/4/8 with both sequen-
tial and interleave mode
Internal four bank operations with single pulsed
/RAS
Auto refresh and self refresh supported
tRAS lock out function supported
8192 refresh cycles / 64ms
JEDEC standard 400mil 66pin TSOP-II with 0.65mm
pin pitch
Full and Half strength driver option controlled by
EMRS
ORDERING INFORMATION
* X means speed grade
Part No.
Configuration
Package
HY5DU56422D(L)T-X*
64M x 4
400mil
66pin
TSOP-II
HY5DU56822D(L)T-X*
32M x 8
HY5DU561622D(L)T-X*
16M x 16
OPERATING FREQUENCY
Grade
Clock Rate
Remark
(CL-tRCD-tRP)
-D43
200MHz@CL3
DDR400B (3-3-3)
- J
133MHz@CL2 166MHz@CL2.5 DDR333 (2.5-3-3)
- K
133MHz@CL2 133MHz@CL2.5 DDR266A (2-3-3)
- H
100MHz@CL2 133MHz@CL2.5 DDR266B (2.5-3-3)
- L
100MHz@CL2
DDR200 (2-2-2)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY5DU56422DT | 256Mb DDR SDRAM |
| HY5DU56822DLT | 256Mb DDR SDRAM |
| HY5DU56822DT | 256Mb DDR SDRAM |
| HY5DU56422BT-D4 | 256M-P DDR SDRAM |
| HY5DU56822BT-D | 256M-P DDR SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY5DU56422DLTP | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU56422DLTP-H | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU56422DLTP-J | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU56422DLTP-K | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU56422DLTP-L | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。