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參數(shù)資料
| 型號： | HY5DU56422CT-D4 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 256M-P DDR SDRAM |
| 中文描述： | 64M X 4 DDR DRAM, 0.65 ns, PDSO66 |
| 封裝： | 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66 |
| 文件頁數(shù)： | 25/34頁 |
| 文件大?。?/td> | 248K |
| 代理商： | HY5DU56422CT-D4 |
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Rev. 0.3 / Oct. 2003 25
HY5DU56422CT-D4/ D43
HY5DU56822CT-D4/ D43
HY5DU561622CT-D4/ D43
DC CHARACTERISTICS II
(TA=0 to 70
o
C, Voltage referenced to V
SS
= 0V)
16Mx16
Parameter
Symbol
Test Condition
Speed
Unit Note
-D4
-D43
Operating Current
IDD0
One bank; Active - Precharge;
tRC=tRC(min); tCK=tCK(min); DQ,DM and
DQS inputs changing twice per clock cycle;
address and control inputs changing once
per clock cycle
120
125
mA
Operating Current
I
DD1
One bank; Active - Read - Precharge;
Burst=2; tRC=tRC(min); tCK=tCK(min);
address and control inputs changing once
per clock cycle; IOUT=0mA
135
140
mA
Precharge Power
Down Standby
Current
I
DD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
10
mA
Idle Standby Current
I
DD2F
/CS=High, All banks idle; tCK=tCK(min);
CKE=High; address and control inputs
changing once per clock cycle.
VIN=VREF for DQ, DQS and DM
55
mA
Active Power Down
Standby Current
I
DD3P
One bank active; Power down mode ;
CKE=Low, tCK=tCK(min)
15
mA
Active Standby
Current
I
DD3N
/CS=HIGH; CKE=HIGH; One bank; Active-
Precharge; tRC=tRAS(max); tCK=tCK(min);
DQ, DM and DQS inputs changing twice per
clock cycle; Address and other control inputs
changing once per clock cycle
65
mA
Operating Current
I
DD4R
Burst=2; Reads; Continuous burst; One bank
active; Address and control inputs changing
once per clock cycle; tCK=tCK(min);
IOUT=0mA
220
mA
Operating Current
I
DD4W
Burst=2; Writes; Continuous burst; One
bank active; Address and control inputs
changing once per clock cycle;
tCK=tCK(min); DQ, DM and DQS inputs
changing twice per clock cycle
280
mA
Auto Refresh Current
I
DD5
tRC=tRFC(min); All banks active
180
mA
Self Refresh Current
I
DD6
CKE=<0.2V; External clock on;
tCK=tCK(min)
Normal
3
mA
Low Power
1.5
mA
Operating Current -
Four Bank Operation
I
DD7
Four bank interleaving with BL=4, Refer to
the following page for detailed test condition
320
mA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY5DU56422CT-D43 | 256M-P DDR SDRAM |
| HY5DU56822CT-D | 256M-P DDR SDRAM |
| HY5DU56822CT-D4 | 256M-P DDR SDRAM |
| HY5DU56822CT-D43 | 256M-P DDR SDRAM |
| HY5DU561622CT-D | 256M-P DDR SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY5DU56422CT-D43 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M-P DDR SDRAM |
| HY5DU56422DLT | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256Mb DDR SDRAM |
| HY5DU56422DLTP | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU56422DLTP-H | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU56422DLTP-J | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
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