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參數(shù)資料
| 型號(hào)： | HY5DU56422BT-D4 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 256M-P DDR SDRAM |
| 中文描述： | 64M X 4 DDR DRAM, 0.7 ns, PDSO66 |
| 封裝： | 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66 |
| 文件頁數(shù)： | 3/32頁 |
| 文件大?。?/td> | 233K |
| 代理商： | HY5DU56422BT-D4 |
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DESCRIPTION
The Hynix HY5DU56422BT ,HY5DU56822BT are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM,
ideally suited for the main memory applications which requires large memory density and high bandwidth.
The Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
PRELIMINARY
Rev. 0.4 / Aug. 2003 3
HY5DU56422BT-D4/ D43
HY5DU56822BT-D4/ D43
V
DD
/V
DDQ
= 2.5 ~ 2.7V
All inputs and outputs are compatible with SSTL_2
interface
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous - data transaction aligned to
bidirectional data strobe (DQS)
x16 device has two bytewide data strobes (UDQS,
LDQS) per each x8 I/O
Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
On chip DLL align DQ and DQS transition with CK
transition
DM mask write data-in at the both rising and falling
edges of the data strobe
All addresses and control inputs except data, data
strobes and data masks latched on the rising edges
of the clock
CAS latency 3 supported
Programmable burst length 2 / 4 / 8 with both
sequential and interleave mode
Internal four bank operations with single pulsed
/RAS
tRAS Lock-out function supported
Auto refresh and Self refresh supported
8192 refresh cycles / 64ms
JEDEC standard 400mil 66pin TSOP-II with 0.65mm
pin pitch
Full and Half strength driver option controlled by
EMRS
ORDERING INFORMATION
* Note : D of speed indicates DDR400.
Part No.
Configuration
Package
HY5DU56822BT-D*
64Mx4
400mil
66pin
TSOP-II
HY5DU56822BT-D*
32Mx8
OPERATING FREQUENCY
Grade
CL3
Remark
(CL-tRCD-tRP)
- D4
200MHz
DDR400 (3-4-4)
- D43
200MHz
DDR400 (3-3-3)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY5DU56822BT-D | 256M-P DDR SDRAM |
| HY5DU56422CT-D | 256M-P DDR SDRAM |
| HY5DU561622CT-D4 | 256M-P DDR SDRAM |
| HY5DU561622CT-D43 | 256M-P DDR SDRAM |
| HY5DU56422CT-D4 | 256M-P DDR SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY5DU56422BT-D4/D43 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M-P DDR SDRAM |
| HY5DU56422CT-D | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M-P DDR SDRAM |
| HY5DU56422CT-D4 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M-P DDR SDRAM |
| HY5DU56422CT-D43 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M-P DDR SDRAM |
| HY5DU56422DLT | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256Mb DDR SDRAM |
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