參數(shù)資料
型號： HUFA76504DK8T
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 功率晶體管
英文描述： 2.3A, 80V, 0.222 Ohm, Dual N-Channel, Logic Level UltraFET Power MOSFET
中文描述： 2500 mA, 80 V, 2 CHANNEL, N-CHANNEL, Si, SMALL SIGNAL, MOSFET, MS-012AA
文件頁數(shù)： 2/13頁
文件大?。?/td> 313K
代理商： HUFA76504DK8T
2001 Fairchild Semiconductor Corporation
Rev. A, June 4, 2001
Electrical Specifications
T
A
= 25
o
C, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
BV
DSS
I
D
= 250
μ
A, V
GS
= 0V (Figure 12)
I
D
= 250
μ
A, V
GS
= 0V , T
A
= -40
o
C (Figure 12)
V
DS
= 75V, V
GS
= 0V
V
DS
= 70V, V
GS
= 0V, T
A
= 150
o
C
V
GS
=
±
16V
80
-
-
V
70
-
-
V
μ
A
μ
A
nA
Zero Gate Voltage Drain Current
I
DSS
-
-
1
-
-
250
±
100
Gate to Source Leakage Current
I
GSS
-
-
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
V
GS(TH)
r
DS(ON)
V
GS
= V
DS
, I
D
= 250
μ
A (Figure 11)
I
D
= 2.5A, V
GS
= 10V (Figures 9, 10)
I
D
=
1.1A, V
GS
= 5V (Figure 9)
I
D
= 1.1A, V
GS
= 4.5V (Figure 9)
1
-
3
V
Drain to Source On Resistance
-
0.173
0.200
-
0.193
0.222
-
0.200
0.230
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Lead
R
θ
JL
R
θ
JA
-
-
25
o
C/W
o
C/W
o
C/W
o
C/W
Thermal Resistance Junction to Ambi-
ent
Pad Area = 0.50 in
2
(323 mm
2
) (Note 2)
Pad Area = 0.027 in
2
(17.4 mm
2
) (Figure 23)
Pad Area = 0.006 in
2
(3.87 mm
2
) (Figure 23)
-
-
50
-
-
191
-
-
228
SWITCHING SPECIFICATIONS
(V
GS
= 4.5V)
Turn-On Time
t
ON
t
d(ON)
t
r
t
d(OFF)
t
f
t
OFF
V
DD
= 40V, I
D
= 1.1A
V
GS
=
4.5V, R
GS
= 43
(Figures 15, 21, 22)
-
-
100
ns
Turn-On Delay Time
-
27
-
ns
Rise Time
-
40
-
ns
Turn-Off Delay Time
-
73
-
ns
Fall Time
-
31
-
ns
Turn-Off Time
-
-
160
ns
SWITCHING SPECIFICATIONS
(V
GS
= 10V)
Turn-On Time
t
ON
t
d(ON)
t
r
t
d(OFF)
t
f
t
OFF
V
DD
= 40V, I
D
= 2.5A
V
GS
=
10V,
R
GS
=
47
(Figures 16, 21, 22)
-
-
41
ns
Turn-On Delay Time
-
10
-
ns
Rise Time
-
18
-
ns
Turn-Off Delay Time
-
115
-
ns
Fall Time
-
36
-
ns
Turn-Off Time
-
-
230
ns
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Q
g(TOT)
Q
g(5)
Q
g(TH)
Q
gs
Q
gd
V
GS
= 0V to 10V
V
GS
= 0V to 5V
V
GS
= 0V to 1V
V
DD
= 40V,
I
D
= 1.1A,
I
g(REF)
= 1.0mA
(Figures 14, 19, 20)
-
6.6
10
nC
Gate Charge at 5V
-
3.4
5.4
nC
Threshold Gate Charge
-
0.3
0.5
nC
Gate to Source Gate Charge
-
0.8
-
nC
Gate to Drain “Miller” Charge
-
1.4
-
nC
CAPACITANCE SPECIFICATIONS
Input Capacitance
C
ISS
C
OSS
C
RSS
V
DS
= 25V, V
GS
= 0V,
f = 1MHz
(Figure 13)
-
270
-
pF
Output Capacitance
-
62
-
pF
Reverse Transfer Capacitance
-
11
-
pF
Source to Drain Diode Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Source to Drain Diode Voltage
V
SD
I
SD
=1.1A
I
SD
= 0.7A
I
SD
=
5.0A, dI
SD
/dt = 100A/
μ
s
I
SD
= 5.0A, dI
SD
/dt = 100A/
μ
s
-
-
1.25
V
-
-
1.00
V
Reverse Recovery Time
t
rr
-
-
62
ns
Reverse Recovered Charge
Q
RR
-
-
115
nC
HUFA76504DK8
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