參數(shù)資料
型號(hào): HTSH4801ETK
廠商: NXP Semiconductors N.V.
元件分類: 通信及網(wǎng)絡(luò)
英文描述: HITAG S transponder IC
封裝: HTSFCH4801EV/DH<SOT732-1 (FCP2)|<<http://www.nxp.com/packages/SOT732-1.html<1<Always Pb-free,;HTSFCH5601EV/DH<SOT732-1 (FCP2)|<<http://www.nxp.com/packages/SOT732-1.html&
文件頁數(shù): 5/21頁
文件大?。?/td> 162K
代理商: HTSH4801ETK
HTSICH56_48_SDS
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product short data sheet
COMPANY PUBLIC
Rev. 3.0 — 12 October 2011
210330
5 of 21
NXP Semiconductors
HTSICH56; HTSICH48
HITAG S transponder IC
7. Functional description
7.1 Memory organization
The EEPROM has a capacity up to 2048 bit and is organized in 16 Blocks, consisting of
4 Pages each, for commands with Block access. A Page consists of 4 Bytes each (1 Page
= 32 Bits) and is the smallest access unit.
Addressing is done Page by Page (Page 0 to 63) and access is gained either Page by
Page or Block by Block entering the respective Page start address. In case of Block
Read/Write access, the transponder is processed from the start Page address within one
block to the end of the corresponding block.
Two different types of HITAG S IC’s with different memory sizes as shown in the figure
above are available.
7.2 HITAG S plain mode
Table 3.
Fig 2.
Memory organization
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x3B
0x3C
0x3D
0x3E
0x3F
page 0
page 1
page 2
page 3
page 4
page 5
page 6
page 7
page 8
page 9
page 10
page 11
page 12
page 13
page 14
page 15
page 16
Page
Address
Block 0
Block 1
Block 2
Block 3
Block 15
32 bit
H56
HITAG S Type
H48
page 59
page 60
page 61
page 62
page 63
aaa-000830
Memory map for HITAG S in plain mode
MSByte
page address
MSB
0x00
LSByte
LSB MSB
LSB MSB
LSB MSB
LSB
UID3
UID2
UID1
UID0
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