
Instruction Set Summary
Mnemonic
Description
F lag Affected
Instruction
Cycle
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to register with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in
data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry with
result in data memory
Decimal adjust ACC for addition with result in
data memory
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
C
1
1
(1)
1
1
1
(1)
1
1
1
(1)
1
1
(1)
1
(1)
Logic
Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
AND data memory to ACC
OR data memory to ACC
E xclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
E xclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1
1
1
(1)
1
(1)
1
(1)
1
1
1
1
(1)
1
Increment &
Decrement
INCA [m]
INC [m]
DE CA [m]
DE C [m]
Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory
Z
Z
Z
Z
1
1
(1)
1
1
(1)
HT48CXX/HT48RXX
29
25th May ’99