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參數(shù)資料
| 型號(hào)： | HSP50306SC-25 |
| 廠商： | INTERSIL CORP |
| 元件分類(lèi)： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Digital QPSK Demodulator |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁(yè)數(shù)： | 3/8頁(yè) |
| 文件大小： | 37K |
| 代理商： | HSP50306SC-25 |
8-274
The Block Diagram of the QPSK Demodulator is shown on
page 1. To demodulate the data, the I.F. samples are multi-
plied by sine and cosine samples from a numerically con-
trolled oscillator. The digital mixer outputs are then low pass
filtered to remove mixer products. The filtered data is then
equalized by a 4 tap equalizer (1 precursor, one reference tap,
and a 2 tap Decision Feedback Equalizer (DFE) to remove
distortion caused by multipath. The output of the equalizer is
differentially decoded and multiplexed into the output data
stream. The carrier tracking loop providing the L.O. for the dig-
ital mixer is a second order digital Costas loop with a tracking
bandwidth of ~10kHz. A sweep circuit searches the carrier
uncertainty using a triangle sweep algorithm during acquisi-
tion. A lock detector controls the sweep and indicates when
valid data is available. The recovered data rate clock is gener-
ated by another numerically controlled oscillator. The timing
recovery loop is a first order decision directed digital phase
locked with a loop bandwidth of
~
3kHz. The Level Detect cir-
cuitry generates the AGC error signal by rectifying the I.F.
input samples and comparing them against a threshold. The
error signal is low if the signal magnitude is above the upper
threshold, high if the magnitude is below the lower limit.
Figure 1 shows the circuit of a typical demodulator
application. The typical Bit Error Rate (BER) performance is
shown in Figure 2 for both 4-bit and 6-bit quantized inputs.
The theoretical QPSK BER Performance Curve is provided for
reference. Note that the BER performance shown in Figure 2
includes a multipath distortion element at the input, in addition
to the desired signal. This multipath distortion is
representative of receive signal distortions found in cable data
links.
Table 1 details the BER, Acquisition and Delay Performance
Specifications of the HSP50306 QPSK demodulator chip,
based on an input that complies with the specifications
detailed in Table 2.
Application Example
OSC
CA3304/6
CLKIN
DIN0-5
ADCLK
AGCOUT
RESET
TEST
CLKOUT
DATAOUT
LOCK
HSP50306
6
I.F. FILTER
V+
A/D
DIGITIZED
10.7MHz (2.1MHz)
IF INPUT
(25.6MHz)
26.97MHz
2.048 MBPS
OUTPUT
DATA/CLK
FIGURE 1. APPLICATIONS CIRCUIT EXAMPLE
0.01
0.001
0.0001
0.00001
1E-06
1E-07
1E-08
1E-09
1E-10
1E-11
1E-12
11
12
13
14
15
16
17
18
19
20
21
22
23
E
S
/N
O
B
NOTE: Simulation performed using alpha = 0.4 Root Raised Cosine Transmit Filtering, Multipath -10dBc at 72
o
at 1.6
μ
s.
FIGURE 2. TYPICAL BIT ERROR RATE PERFORMANCE
4-BIT DATA
6-BIT DATA
THEORETICAL
HSP50306
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HSP50306SC-2596 | Digital QPSK Demodulator |
| HSP50306SC-27 | Digital QPSK Demodulator |
| HSP50306SC-2796 | Digital QPSK Demodulator |
| HSP50306 | Digital QPSK Demodulator(數(shù)字QPSK解調(diào)器) |
| HSP9501JC-25 | Programmable Data Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP50306SC-2596 | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Digital QPSK Demodulator |
| HSP50306SC-27 | 制造商:Rochester Electronics LLC 功能描述:QPSK DEMODULATOR 16 LEAD SOIC - Bulk |
| HSP50306SC-27 WAF | 制造商:Intersil Corporation 功能描述: |
| HSP50306SC-2796 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50307 | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Burst QPSK Modulator |
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