參數(shù)資料
型號(hào)： HS9-82C54RH
廠商： Intersil Corporation
英文描述： Radiation Hardened CMOS Programmable Interval Timer
中文描述： 輻射加固CMOS可編程間隔定時(shí)器
文件頁數(shù)： 4/21頁
文件大?。?/td> 171K
代理商： HS9-82C54RH
951
Specifications HS-82C54RH
Command Recovery Time
TRHRL
VDD = 4.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
320
-
ns
WRITE CYCLE
Address Stable Before WR
TAVWL
VDD = 4.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
0
-
ns
CS Stable Before WR
TSLWL
VDD = 4.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
0
-
ns
Address Hold Time After WR
TWHAX
VDD = 4.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
0
-
ns
WR Pulse Width
TWLWH
VDD = 4.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
240
-
ns
Data Setup Time Before WR
TDVWH
VDD = 4.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
225
-
ns
Data Hold Time After WR
TWHDX
VDD = 4.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
35
-
ns
Command Recovery Time
TWHWL
VDD = 4.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
320
-
ns
CLOCK AND GATE
Clock Period
TCLCL
VDD = 4.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
200
-
ns
High Pulse Width
TCHCL
VDD = 4.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
100
-
ns
Low Pulse Width
TCLCH
VDD = 4.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
100
-
ns
Gate Width High
TGHGL
VDD = 4.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
80
-
ns
Gate Width Low
TGLGH
VDD = 4.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
80
-
ns
Gate Setup Time to CLK
TGVCH
VDD = 4.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
80
-
ns
Gate Hold Time After CLK
TCHGX
VDD = 4.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
80
-
ns
Output Delay from CLK
TCLOV
VDD = 4.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
-
240
ns
Output Delay from Gate
TGLOV
VDD = 4.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
-
200
ns
Data Delay from Address Read
TAVAV
VDD = 4.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
-
275
ns
Output Delay from WR High
TWHOV
VDD = 4.5V
9, 10, 11
-55
o
C, +25
o
C, +125
o
C
-
260
ns
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS
TEMPERATURE
LIMITS
UNITS
MIN
MAX
Input Capacitance
CIN
VDD = Open, f = 1MHz,
All measurements referenced to device ground.
T
A
= +25
o
C
-
15
pF
Output Capacitance
COUT
VDD = Open, f = 1MHz,
All measurements referenced to device ground.
T
A
= +25
o
C
-
15
pF
I/O Capacitance
COUT
VDD = Open, f = 1MHz,
All measurements referenced to device ground.
T
A
= +25
o
C
-
20
pF
TIMING REQUIREMENTS
RD/ to Data Float
TRHDZ
VDD = 4.5V and 5.5V
-55
o
C < T
A
< +125
o
C
8
145
ns
TIMING RESPONSES
Clock Rise Time
TCH1CH2
VDD = 4.5V and 5.5V, 1.0V to 3.5V
-55
o
C < T
A
< +125
o
C
-55
o
C < T
A
< +125
o
C
-
25
ns
Clock Fall Time
TCL1CL2
VDD = 4.5V and 5.5V, 3.5V to 1.0V
-
25
ns
NOTE: The parameters listed are controlled via design or process parameters and are not directly tested. These parameters are character-
ized upon initial design release and upon design changes which would affect these characteristics.
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
AC’s Tested at Worst Case VDD (s), Guaranteed Over Full Operating Range.
PARAMETER
SYMBOL
CONDITIONS
GROUP A
SUBGROUPS
TEMPERATURE
LIMITS
UNITS
MIN
MAX
Spec Number
518059
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