參數(shù)資料
型號(hào)： HS1-82C54RH
廠商： Intersil Corporation
英文描述： Radiation Hardened CMOS Programmable Interval Timer
中文描述： 輻射加固CMOS可編程間隔定時(shí)器
文件頁(yè)數(shù)： 16/21頁(yè)
文件大?。?/td> 171K
代理商： HS1-82C54RH
963
HS-82C54RH
with the new count and the one-shot pulse continues until
the new count expires.
NOTES:
1. Counters are programmed for binary (not BCD) counting and for
reading/writing least significant byte (LSB) only.
2. The Counter is always selected (CS always low).
3. CW stands for “Control Word”; CW = 10 means a Control Word
of 10, Hex is written to the Counter.
4. LSB stands for “Least significant byte” of count.
5. Numbers below diagrams are count values. The lower number is
the least significant byte. The upper number is the most signifi-
cant byte. Since the Counter is programmed to read/write LSB
only, the most significant byte cannot be read.
6. N stands for an undefined count.
7. Vertical lines show transitions between count values.
FIGURE 18. MODE 1
Mode 2: Rate Generator
This Mode functions like a divide-by-N counter. It is typically
used to generate a Real Time Clock interrupt. OUT will
initially be high. When the initial count has decremented to 1,
OUT goes low for one CLK pulse. OUT then goes high
again, the Counter reloads the initial count and the process
is repeated. Mode 2 is periodic; the same sequence is
repeated indefinitely. For an initial count of N, the sequence
repeats every N CLK cycles.
GATE = 1 enables counting; GATE = 0 disables counting. If
GATE goes low during an output pulse, OUT is set high
immediately. A trigger reloads the Counter with the initial
count on the next CLK pulse; OUT goes low N CLK pulses
after the trigger. Thus the GATE input can be used to
synchronize the Counter.
WR
CLK
GATE
OUT
WR
CLK
GATE
OUT
WR
CLK
GATE
OUT
CW = 12
LSB = 3
CW = 12
LSB = 3
CW = 12
LSB = 2
LSB = 4
N
N
N
N
N
0
3
0
2
0
1
0
0
FF
FF
0
3
0
2
N
N
N
N
N
0
3
0
2
0
1
0
3
0
2
0
1
0
0
N
N
N
N
N
0
2
0
1
0
0
FF
FF
FF
FE
0
4
0
3
After writing a Control Word and initial count, the Counter will
be loaded on the next CLK pulse. OUT goes low N CLK
pulses after the initial count is written. This allows the
Counter to be synchronized by software also.
Writing a new count while counting does not affect the
current counting sequence. If a trigger is received after
writing a new count but before the end of the current period,
the Counter will be loaded with the new count on the next
CLK pulse and counting will continue from the new count.
Otherwise, the new count will be loaded at the end of the
current counting cycle.
NOTES:
1. Counters are programmed for binary (not BCD) counting and for
reading/writing least significant byte (LSB) only.
2. The Counter is always selected (CS always low).
3. CW stands for “Control Word”; CW = 10 means a Control Word
of 10, Hex is written to the Counter.
4. LSB stands for “Least significant byte” of count.
5. Numbers below diagrams are count values. The lower number is
the least significant byte. The upper number is the most signifi-
cant byte. Since the Counter is programmed to read/write LSB
only, the most significant byte cannot be read.
6. N stands for an undefined count.
7. Vertical lines show transitions between count values.
FIGURE 19. MODE 2
Mode 3: Square Wave Mode
Mode 3 is typically used for Baud rate generation. Mode 3 is
similar to Mode 2 except for the duty cycle of OUT. OUT will
initially be high. When half the initial count has expired, OUT
goes low for the remainder of the count. Mode 3 is periodic;
the sequence above is repeated indefinitely. An initial count
of N results in a square wave with a period of N CLK cycles.
N
N
N
N
0
2
0
1
0
3
0
2
CW = 14 LSB = 3
WR
CLK
GATE
OUT
N
N
N
N
0
2
0
2
0
3
0
2
0
1
CW = 12 LSB = 3
WR
CLK
GATE
OUT
N
N
N
N
0
3
0
2
0
1
CW = 14 LSB = 4
WR
CLK
GATE
OUT
LSB = 5
0
3
0
3
0
5
0
4
0
4
0
1
0
3
0
3
0
3
Spec Number
518059
相關(guān)PDF資料
PDF描述
HS9-82C54RH Radiation Hardened CMOS Programmable Interval Timer
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HS9-82C54RH-8 Radiation Hardened CMOS Programmable Interval Timer
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HS1-82C54RH/PROTO 制造商:Intersil Corporation 功能描述:RAD HARD CMOS PROGRAMMABLE INTERVAL TIMER,PROTO,CLASS V - Rail/Tube
HS1-82C54RH-8 制造商:Intersil Corporation 功能描述:PROGRAMMABLE TIMER SGL 24PIN SBDIP - Rail/Tube
HS1-82C54RH-Q 制造商:Intersil Corporation 功能描述:PROGRAMMABLE TIMER SGL 24PIN SBCDIP - Rail/Tube
HS1-82C55ARH 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened CMOS Programmable Peripheral Interface
HS1-82C55ARH-8 制造商:Intersil Corporation 功能描述:RAD HARD CMOS PROGRAMMABLE PERIPHERAL INTERFACE,DIP,CLS Q - Rail/Tube
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