參數(shù)資料
型號: HMP8117CNZ
廠商: INTERSIL CORP
元件分類: 顏色信號轉換
英文描述: NTSC/PAL Video Decoder
中文描述: COLOR SIGNAL DECODER, PDSO80
封裝: PLASTIC, MS-022GB-1, MQFP-80
文件頁數(shù): 44/45頁
文件大?。?/td> 552K
代理商: HMP8117CNZ
44
FN4643.3
April 19, 2007
GENLOCK PERFORMANCE
Horizontal Locking Time
t
LOCK
Time from Initial Lock
Acquisition to an Error of
1 Pixel. (Note 42)
2
3
Fields
Long-Term horizontal Sync
Lock Range
Range over specified pixel jitter is
maintained. Assumes line time changes
by amount indicated slowly between
over one field. (Note 42)
± -
5
%
Number of Missing Horizontal Syncs
Before Lost Lock Declared
H
SYNC LOST
Programmable via register 04
H
(Note 42)
1 or 12
1 or 12
1 or 12
HSYNCs
Number of Missing Vertical Syncs
Before Lost Lock Declared
V
SYNC LOST
1 or 3
1 or 3
1 or 3
VSYNCs
Long-Term Color Subcarrier
Lock Range
Range over color subcarrier locking
time and accuracy specifications are
maintained. Subcarrier frequency
changes by amount indicated slowly
over 24 hours. (Note 42)
±
200
±
400
Hz
Vertical Sample Alignment
(Notes 42, 44)
1/8
Pixel
10
ns
NOTES:
42. Guaranteed by design or characterization.
43. Test performed with C
L
= 40pF, I
OL
= 4mA, I
OH
= -4mA. Input reference level is 1.5V for all inputs. V
IH
= 3.0V, V
IL
= 0V.
44. Since the HMP8117 does not generate the sample clock, any clock jitter present on the CLK2 input will directly translate to pixel jitter on the
output data. The Vertical Sample Alignment parameter specifies the spatial pixel alignment from one scan line to the next using a stable CLK2
source.
Electrical Specifications
V
CC
= V
AA
= 5.0V, T
A
= +25°C
(Continued)
PARAMETER
SYMBOL
TEST CONDITION
MIN
TYP
MAX
UNITS
HMP8117
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