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參數資料
| 型號： | HIP0045AB |
| 廠商： | INTERSIL CORP |
| 元件分類： | 外設及接口 |
| 英文描述： | ;Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No RoHS Compliant: No |
| 中文描述： | 1.4 A LATCH BASED PRPHL DRVR, PDSO20 |
| 封裝： | POWER, PLASTIC, SOP-20 |
| 文件頁數： | 5/10頁 |
| 文件大小： | 93K |
| 代理商： | HIP0045AB |
4-5
Data Valid Time, SCK to Data at MISO Valid
t
V
V
CC
= 5V
±
0.1V
-
-
100
ns
Time for SCK Low before CE Low (SCK Setup Time
before CE High to Low Change)
t
SCK_LEAD
100
-
-
ns
Time for SCK High after CE High
t
SCK_LAG
150
-
-
ns
CE Pulse Filter Time
-
Note 9
-
ns
NOTES:
7. The MOSFET Output Drain is internally clamped with a Drain-to-Gate zener diode that turns-on the MOSFET; holding the Drain at the Output
Clamp Voltage, V
OC
.
8. The measurement of Output Leakage Current includes the Output Pull-Down Current, I
SK
. Each Output has a Current Pull-Down which is used
to detect open load fault conditions.
9. The digital filter time for the output latch function determines if the output latch function will be enabled. The output latch function will only be
enabled if a positive CE slope occurs after 8 SCK clock cycles or a multiple of 8 SCK cycles since the last CE negative slope change.
Serial Peripheral Interface Timing
(MOSI, MISO Load Capacitor = 100pF, See Figure 1)
PARAMETER
SYMBOL
TEST CONDITION
MIN
TYP
MAX
UNITS
Timing Diagrams
FIGURE 1A. DATA AND CLOCK TIMING DIAGRAM
FIGURE 1B. SPI TIMING DIAGRAM
CE
SCK
MSB 6 5 4 3 2 1 LSB
(CPOL = 0, CPHA = 1)
INTERNAL STROBE FOR DATA CAPTURE
CE
(INPUT)
SCK
(INPUT)
MISO
(OUTPUT)
MOSI
(INPUT)
DRIVER
OUTPUT
HIGH
Z
LAST BIT
TRANSMITTED
D7O
D6O
D0O
D7I
D6I
D0I
OLD
FAULT-INDUCED
TURN-OFF
t
DON
t
DOFF
t
DF
t
DIS
t
V
t
LAG
t
H
t
SU
t
WSCKL
t
WSCKH
t
LEAD
t
EN
NEW
HIP0045
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