參數(shù)資料
型號(hào)： HIP0045AB
廠商： INTERSIL CORP
元件分類： 外設(shè)及接口
英文描述： ;Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No RoHS Compliant: No
中文描述： 1.4 A LATCH BASED PRPHL DRVR, PDSO20
封裝： POWER, PLASTIC, SOP-20
文件頁數(shù)： 4/10頁
文件大?。?/td> 93K
代理商： HIP0045AB
4-4
Open Load Threshold Voltage
V
REF
Open Load Fault Condition, Fault Detected If
V
OUT
< V
REF
0.32 x
V
CC
-
0.4x
V
CC
V
Open Load Pull-Down Current
I
SK
No Load, V
OUT
= V
BATT
= 16V
20
-
100
μ
A
Over-CurrentShutdownThreshold,OUT0-5
I
SC
V
CC
= 5V
1.05
1.4
2
A
Short Circuit Current Limit, OUT6, 7
I
LIM
V
CC
= 5V
1.05
1.4
1.75
A
Short Circuit Shutdown Delay, OUT0 - 5
t
SC
0.2
-
12
μ
s
DisableFaultDetectionTime,ChannelIN0,
IN1 After Input Switch Transition
t
DF
15
-
50
μ
s
Over-Temperature Detection Threshold
T
OFF
155
165
175
o
C
LOGIC INPUTS (IN0, IN1, MOSI, SCK, RESET, CE)
Threshold Voltage at Falling Edge
V
T
-
0.2xV
CC
-
-
V
Threshold Voltage at Rising Edge
V
T
+
-
-
0.7xV
CC
V
Hysteresis Voltage
V
H
V
T
+ - V
T
-
0.65
-
-
V
Input Current
I
IN
V
IN
= V
CC
-
-
+10
μ
A
Input Pull-Up Resistance
R
IN
50
80
200
k
Input Capacitance
C
IN
-
-
10
pF
Input Frequency, IN0, IN15
f
IN
DC
-
2
kHz
Active Supply Range for Reset State
Change at RESET Pin
V
HCC_RS
T
RESET Pin Forced Reset. (Note: Normal V
CC
Functional Operating Range is 4.0V to 5.5V)
3.1
-
5.5
V
Low V
CC
Active Reset Threshold
V
LCC_RST
Low V
CC
Forced Reset, (Low Voltage Reset
Active for 0 < V
CC
< V
LCC_RST
)
3.1
-
4
V
LOGIC OUTPUT (MISO)
Data Output LOW Voltage
V
SOL
I
SO
= -3.2mA
-
0.2
0.4
V
Data Output HIGH Voltage
V
SOH
I
SO
= -4mA
V
CC
-
0.4V
-
-
V
Output Three-State Leakage Current
I
SOL
CE = High, 0V
≤
V
SO
≤
V
CC
-10
-
+10
μ
A
Output Capacitance
C
SO
f
OPER
= 3MHz
-
-
10
pF
Electrical Specifications
V
CC
= 4.5V to 5.5V, T
A
= -40
o
C to 125
o
C, Unless Otherwise Specified
(Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Serial Peripheral Interface Timing
(MOSI, MISO Load Capacitor = 100pF, See Figure 1)
PARAMETER
SYMBOL
TEST CONDITION
MIN
TYP
MAX
UNITS
Clock Frequency, 50% Duty Cycle
f
CLK
3
-
-
MHz
Enable Lead Time
(SCK Change Low to High after CE = Low)
t
LEAD
100
-
-
ns
Enable Lag Time
(Time for SCK Low before CE goes High)
t
LAG
150
-
-
ns
Minimum Time SCK = High
t
WSCKH
160
-
-
ns
Minimum Time SCK = Low
t
WSCKL
160
-
-
ns
Data Setup Time (SCK Change from High to Low
after MOSI Data Valid)
t
SU
20
-
-
ns
Data Hold Time (MOSI Data Hold Time SCK
Change from High to Low)
t
H
-
20
ns
Enable Time from CE = Low to Data at MISO
t
EN
-
-
100
ns
Disable Time
(Time for CE Low to High to Output Data Float)
t
DIS
-
-
100
ns
HIP0045
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PDF描述
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