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參數(shù)資料
| 型號(hào)： | HI7190 |
| 廠商： | Intersil Corporation |
| 英文描述： | 24-Bit, High Precision, Sigma Delta A/D Converter(24位高精密∑-Δ A/D轉(zhuǎn)換器) |
| 中文描述： | 24位，精度高，Σ-ΔA / D轉(zhuǎn)換（24位高精密Σ-Δ的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 13/25頁 |
| 文件大?。?/td> | 472K |
| 代理商： | HI7190 |
13
FN3612.10
June 27, 2006
should be mid-scale (800000
h
). Instead, there is a small
probability, of an erroneous negative full scale (000000
h
)
output. Refer to Technical Brief TB348 for complete
details.
The FP10 to FP0 bits programmed into the Control Register
determine the cutoff (or notch) frequency of the digital filter.
The allowable code range is 00A
H
. This corresponds to a
maximum and minimum cutoff frequency of 1.953kHz and
10Hz, respectively when operating at a clock frequency of
10MHz. If a 1MHz clock is used then the maximum and
minimum cutoff frequencies become 195.3kHz and 1Hz,
respectively. A plot of the (sinx/x)
3
digital filter characteristics
is shown in Figure 9. This filter provides greater than 120dB
of 50Hz or 60Hz rejection. Changing the clock frequency or
the programming of the FP bits does not change the shape
of the filter characteristics, it merely shifts the notch
frequency. This low pass digital filter at the output of the
converter has an accompanying settling time for step inputs
just as a low pass analog filter does. New data takes
between 3 and 4 conversion periods to settle and update on
the serial port with a conversion period t
CONV
being equal to
1/f
N
.
Input Filtering
The digital filter does not provide rejection at integer
multiples of the modulator sampling frequency. This implies
that there are frequency bands where noise passes to the
output without attenuation. For most cases this is not a
problem because the high oversampling rate and noise
shaping characteristics of the modulator cause this noise to
become a small portion of the broadband noise which is
filtered. However, if an anti-alias filter is necessary a single
pole RC filter is usually sufficient.
If an input filter is used the user must be careful that the source
impedance of the filter is low enough not to cause gain errors in
the system. The DC input impedance at the inputs is > 1G
Ω
but
it is a dynamic load that changes with clock frequency and
selected gain. The input sample rate, also dependent upon
clock frequency and gain, determines the allotted time for the
input capacitor to charge. The addition of external components
may cause the charge time of the capacitor to increase beyond
the allotted time. The result of the input not settling to the proper
value is a system gain error which can be eliminated by system
calibration of the HI7190.
Clocking/Oscillators
The master clock into the HI7190 can be supplied by either a
crystal connected between the OSC
1
and OSC
2
pins as
shown in Figure 10A or a CMOS compatible clock signal
connected to the OSC
1
pin as shown in Figure 10B. The
input sampling frequency, modulator sampling frequency,
filter -3dB frequency, output update rate, and calibration time
are all directly related to the master clock frequency, f
OSC
.
For example, if a 1MHz clock is used instead of a 10MHz
clock, what is normally a 10Hz conversion rate becomes a
1Hz conversion rate. Lowering the clock frequency will also
lower the amount of current drawn from the power supplies.
Please note that the HI7190 specifications are written for a
10MHz clock only.
Operational Modes
The HI7190 contains several operational modes including
calibration modes for cancelling offset and gain errors of
both internal and external circuitry. A calibration routine
should be initiated whenever there is a change in the
ambient operating temperature or supply voltage. Calibration
should also be initiated if there is a change in the gain, filter
notch, bipolar, or unipolar input range. Non-calibrated data
can be obtained from the device by writing 000000 to the
Offset Calibration Register, 800000 (h) to the Positive Full
Scale Calibration Register, and 800000 (h) to the Negative
Full Scale Calibration Register. This sets the offset
correction factor to 0 and both the positive and negative gain
slope factors to 1.
ALIAS BAND
f
N
±
f
C
FREQUENCY (Hz)
A
f
N
f
C
2f
N
3f
N
4f
N
0
-20
-40
-60
-80
-100
-120
FIGURE 9. LOW PASS FILTER FREQUENCY CHARACTERISTICS
FIGURE 10A.
FIGURE 10B.
FIGURE 10. OSCILLATOR CONFIGURATIONS
HI7190
OSC
1
OSC
2
10MHz
16
17
HI7190
OSC
1
OSC
2
10MHz
16
17
NO
CONNECTION
HI7190
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