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參數(shù)資料
| 型號： | HI7190 |
| 廠商： | Intersil Corporation |
| 英文描述： | 24-Bit, High Precision, Sigma Delta A/D Converter(24位高精密∑-Δ A/D轉(zhuǎn)換器) |
| 中文描述： | 24位，精度高，Σ-ΔA / D轉(zhuǎn)換（24位高精密Σ-Δ的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 11/25頁 |
| 文件大小： | 472K |
| 代理商： | HI7190 |
11
FN3612.10
June 27, 2006
junction. The feedback loop forces the average of the fed
back signal to be equal to the input signal V
IN
.
Analog Inputs
The analog input on the HI7190 is a fully differential input
with programmable gain capabilities. The input accepts both
unipolar and bipolar input signals and gains range from 1 to
128. The common mode range of this input is from AV
SS
to
AV
DD
provided that the absolute value of the analog input
voltage lies within the power supplies. The input impedance
of the HI7190 is dependent upon the modulator input
sampling rate and the sampling rate varies with the selected
PGIA gain. Table 3 shows the sampling rates and input
impedances for the different gain settings of the HI7190.
Note that this table is valid only for a 10MHz master clock. If
the input clock frequency is changed, then the input
impedance will change accordingly. The equation used to
calculate the input impedance is:
where C
in
is the nominal input capacitance (8pF) and f
S
is
the modulator sampling rate.
Bipolar/Unipolar Input Ranges
The input on the HI7190 can accept either unipolar or bipolar
input voltages. Bipolar or unipolar options are chosen by
programming the B/U bit of the Control Register.
Programming the part for either unipolar or bipolar operation
does not change the input signal conditioning.
The inputs are differential, and as a result are referenced to the
voltage on the V
INLO
input. For example, if V
INLO
is +1.25V
and the HI7190 is configured for unipolar operation with a gain
of 1 and a V
REF
of +2.5V, the input voltage range on the V
INHI
input is +1.25V to +3.75V. If V
INLO
is +1.25V and the HI7190 is
configured for bipolar mode with gain of 1 and a V
REF
of +2.5V,
the analog input range on the V
INHI
input is -1.25V to +3.75V.
Programmable Gain Instrumentation Amplifier
The Programmable Gain Instrumentation Amplifier allows the
user to directly interface low level sensors and bridges directly
to the HI7190. The PGIA has 4 selectable gain options of 1, 2,
4, 8 which are implemented by multiple sampling of the input
signal. Input signals can be gained up further to 16, 32, 64 or
128. These higher gains are implemented in the digital section
of the design to maintain a high signal to noise ratio through
the front end amplifiers. The gain is digitally programmable in
the Control Register via the serial interface. For optimum
PGIA performance the V
CM
pin should be tied to the mid point
of the analog supplies.
Differential Reference Input
The reference inputs of the of the HI7190, V
RHI
and V
RLO
,
provide a differential reference input capability. The nominal
differential voltage (V
REF
= V
RHI
- V
RLO
) is +2.5V and the
common mode voltage cab be anywhere between AV
SS
and
AV
DD
. Larger values of V
REF
can be used without
degradation in performance with the maximum reference
voltage being V
REF
= +5V. Smaller values of V
REF
can also
be used but performance will be degraded since the LSB
size is reduced.
The full scale range of the HI7190 is defined as:
and V
RHI
must always be greater than V
RLO
for proper
operation of the device.
The reference inputs provide a high impedance dynamic
load similar to the analog inputs and the effective input
impedance for the reference inputs can be calculated in the
same manner as it is for the analog input impedance. The
only difference in the calculation is that C
IN
for the reference
inputs is 10.67pF. Therefore, the input impedance range for
the reference inputs is from 149k
Ω
in a gain of 8 or higher
mode to 833k
Ω
in the gain of 1 mode.
V
CM
Input
The voltage at the V
CM
input is the voltage that the internal
analog circuitry is referenced to and should always be tied to
the midpoint of the AV
DD
and AV
SS
supplies. This point
provides a common mode input voltage for the internal
operational amplifiers and must be driven from a low noise,
low impedance source if it is not tied to analog ground.
Failure to do so will result in degraded HI7190 performance.
It is recommended that V
CM
be tied to analog ground when
operating off of AV
DD
= +5V and AV
SS
= -5V supplies.
V
CM
also determines the headroom at the upper and lower
ends of the power supplies which is limited by the common
mode input range where the internal operational amplifiers
remain in the linear, high gain region of operation. The
HI7190 is designed to have a range of AV
SS
+1.8V < V
CM
<
TABLE 3. EFFECTIVE INPUT IMPEDANCE vs GAIN
GAIN
SAMPLING RATE
(kHz)
INPUT IMPEDANCE
(M
Ω
)
1
78.125
1.6
2
156.25
0.8
4
312.5
0.4
8, 16, 32, 64, 128
625
0.2
PGIA
INTEGRATOR
COMPARATOR
V
RHI
V
RLO
DAC
V
IN
+
-
∫
∑
+
-
FIGURE 6. SIMPLE MODULATOR BLOCK DIAGRAM
Z
IN
= 1/(C
IN
x f
S
),
FSR
BIPOLAR
= 2 x V
REF
/GAIN
FSR
UNIPOLAR
= V
REF
/GAIN
HI7190
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