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參數(shù)資料
| 型號(hào)： | HI5813KIJ |
| 廠商： | INTERSIL CORP |
| 元件分類(lèi)： | ADC |
| 英文描述： | CMOS 3.3V, 25 Microsecond, 12-Bit, Sampling A/D Converter with Internal Track and Hold |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP24 |
| 封裝： | CERDIP-24 |
| 文件頁(yè)數(shù)： | 9/11頁(yè) |
| 文件大?。?/td> | 153K |
| 代理商： | HI5813KIJ |
6-1810
The DRDY (Data Ready) status output goes high (specified
by t
D1
DRDY) after the start of clock period 1, and returns
low (specified by t
D2
DRDY) after the start of clock period 2.
The 12 data bits are available in parallel on three-state bus
driver outputs. When low, the OEM input enables the most
significant byte (D4 through D11) while the OEL input
enables the four least significant bits (D0 - D3). t
EN
and t
DIS
specify the output enable and disable times.
If the output data is to be latched externally, either the trailing
edge of data ready or the next falling edge of the clock after
data ready goes high can be used.
Figure 2 shows operation of the HI5813 when the STRT pin
is used to initate a conversion. If STRT is taken high at least
t
R
STRT before clock period 1 and is not reapplied during
that period, the converter will stay in the track mode and the
DRDY output will remain high. A low signal applied to STRT
will bring the DRDY flag low and the conversion will continue
with clock period 3 on the first positive going clock edge that
meets the t
SU
STRT setup time.
Clock
The clock used to drive the HI5813 can range in frequency
from 50kHz up to 750kHz. All converter functions are syn-
chronized with the rising edge of the clock signal. The clock
can be shut off only during the sample (track) portion of the
conversion cycle. At other times it must be above the mini-
mum frequency shown in the specifications. In the above two
cases, a further restriction applies in that the clock should
not be shut off during the third sample period for more than
1ms. This might cause an internal charge pump voltage to
decay.
If the clock is shut off during the conversion time (clock
cycles 4 through 15) of the A/D, the output might be invalid
due to balancing capacitor droop.
The clock must also meet the minimum t
LOW
and t
HIGH
times shown in the specifications. A violation may cause an
internal miscount and invalidate the results.
Power Supplies and Grounding
V
DD
and V
SS
are the digital supply pins: they power all
internal logic and the output drivers. Because the output
drivers can cause fast current spikes in the V
DD
and V
SS
lines, V
SS
should have a low impedance path to digital
ground and V
DD
should be well bypassed.
Except for V
AA
+, which is a substrate connection to V
DD
, all
pins have protection diodes connected to V
DD
and V
SS
.
Input transients above V
DD
or below V
SS
will get steered to
the digital supplies.
The V
AA
+ and V
AA
- terminals supply the charge balancing
comparator only. Because the comparator is autobalanced
between conversions, it has good low frequency supply
rejection. It does not reject well at high frequencies however;
V
AA
- should be returned to a clean analog ground and V
AA
+
should be RC decoupled from the digital supply as shown in
Figure 13.
There is approximately 50
of substrate impedance
between V
DD
and V
AA
+. This can be used, for example, as
part of a low pass RC filter to attenuate switching supply
noise. A 10
μ
F capacitor from V
AA
+ to ground would
attenuate 30kHz noise by approximately 40dB. Note that
back to back diodes should be placed from V
DD
to V
AA
+ to
handle supply to capacitor turn-on or turn-off current spikes.
Dynamic Performance
Fast Fourier Transform (FFT) techniques are used to
evaluate the dynamic performance of the A/D. A low distor-
tion sine wave is applied to the input of the A/D converter.
The input is sampled by the A/D and its output stored in
RAM. The data is than transformed into the frequency
domain with a 4096 point FFT and analyzed to evaluate the
converters dynamic performance such as SNR and THD.
See typical performance characteristics.
Signal-To-Noise Ratio
The signal to noise ratio (SNR) is the measured RMS signal
to RMS sum of noise at a specified input and sampling
frequency. The noise is the RMS sum of all except the
fundamental and the first five harmonic signals. The SNR is
dependent on the number of quantization levels used in the
converter. The theoretical SNR for an N-bit converter with
no differential or integral linearity error is: SNR = (6.02N +
1.76)dB. For an ideal 12-bit converter the SNR is 74dB. Dif-
ferential and integral linearity errors will degrade SNR:
Signal-To-Noise + Distortion Ratio
SINAD is the measured RMS signal to RMS sum of noise
plus harmonic power and is expressed by the following:
Effective Number of Bits
The effective number of bits (ENOB) is derived from the
SINAD data:
Total Harmonic Distortion
The total harmonic distortion (THD) is the ratio of the RMS
sum of the second through sixth harmonic components to
the fundamental RMS signal for a specified input and
sampling frequency.
Spurious-Free Dynamic Range
The spurious-free dynamic range (SFDR) is the ratio of the
fundamental RMS amplitude to the rms amplitude of the next
largest spur or spectral component. If the harmonics are
buried in the noise floor it is the largest peak.
SNR = 10 Log
Sinewave Signal Power
Total Noise Power
SINAD = 10 Log
Sinewave Signal Power
Noise + Harmonic Power (2nd - 6th)
ENOB =
SINAD - 1.76
6.02
THD = 10 Log
Total Harmonic Power (2nd - 6th Harmonic)
Sinewave Signal Power
SFDR = 10 Log
Sinewave Signal Power
Highest Spurious Signal Power
HI5813
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HI5813KIP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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| HI5816KIP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HI5828 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:12-Bit, 125+MSPS, CommLink⑩ Dual High Speed CMOS D/A (2.7V-5.5V) |
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